Description: CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG
To Search:
- [DTXS] - Verilog HDL, prepared by four digital tu
- [LED2] - To improve the digital display lights in
- [4LED] - Experimental steps: 1. Open-wei Fu V3.20
- [CuRT_v1.tar] - Taiwan Niu Jserv of embedded RTOS works
- [chenggong] - To achieve a 4 decimal digits (including
File list (Check if you may need any files):
shumaguan
.........\db
.........\..\div.asm.qmsg
.........\..\div.asm_labs.ddb
.........\..\div.cbx.xml
.........\..\div.cmp.cdb
.........\..\div.cmp.hdb
.........\..\div.cmp.kpt
.........\..\div.cmp.logdb
.........\..\div.cmp.rdb
.........\..\div.cmp.tdb
.........\..\div.cmp0.ddb
.........\..\div.dbp
.........\..\div.db_info
.........\..\div.eco.cdb
.........\..\div.fit.qmsg
.........\..\div.hier_info
.........\..\div.hif
.........\..\div.map.cdb
.........\..\div.map.hdb
.........\..\div.map.logdb
.........\..\div.map.qmsg
.........\..\div.pre_map.cdb
.........\..\div.pre_map.hdb
.........\..\div.psp
.........\..\div.rtlv.hdb
.........\..\div.rtlv_sg.cdb
.........\..\div.rtlv_sg_swap.cdb
.........\..\div.sgdiff.cdb
.........\..\div.sgdiff.hdb
.........\..\div.signalprobe.cdb
.........\..\div.sld_design_entry.sci
.........\..\div.sld_design_entry_dsc.sci
.........\..\div.syn_hier_info
.........\..\div.tan.qmsg
.........\..\hao.asm.qmsg
.........\..\hao.asm_labs.ddb
.........\..\hao.cbx.xml
.........\..\hao.cmp.cdb
.........\..\hao.cmp.hdb
.........\..\hao.cmp.kpt
.........\..\hao.cmp.logdb
.........\..\hao.cmp.rdb
.........\..\hao.cmp.tdb
.........\..\hao.cmp0.ddb
.........\..\hao.dbp
.........\..\hao.db_info
.........\..\hao.eco.cdb
.........\..\hao.fit.qmsg
.........\..\hao.hier_info
.........\..\hao.hif
.........\..\hao.map.cdb
.........\..\hao.map.hdb
.........\..\hao.map.logdb
.........\..\hao.map.qmsg
.........\..\hao.pre_map.cdb
.........\..\hao.pre_map.hdb
.........\..\hao.psp
.........\..\hao.rtlv.hdb
.........\..\hao.rtlv_sg.cdb
.........\..\hao.rtlv_sg_swap.cdb
.........\..\hao.sgdiff.cdb
.........\..\hao.sgdiff.hdb
.........\..\hao.signalprobe.cdb
.........\..\hao.sld_design_entry.sci
.........\..\hao.sld_design_entry_dsc.sci
.........\..\hao.smp_dump.txt
.........\..\hao.syn_hier_info
.........\..\hao.tan.qmsg
.........\..\jishuqi.asm.qmsg
.........\..\jishuqi.cbx.xml
.........\..\jishuqi.cmp.cdb
.........\..\jishuqi.cmp.hdb
.........\..\jishuqi.cmp.kpt
.........\..\jishuqi.cmp.logdb
.........\..\jishuqi.cmp.rdb
.........\..\jishuqi.cmp.tdb
.........\..\jishuqi.cmp0.ddb
.........\..\jishuqi.dbp
.........\..\jishuqi.db_info
.........\..\jishuqi.eco.cdb
.........\..\jishuqi.fit.qmsg
.........\..\jishuqi.hier_info
.........\..\jishuqi.hif
.........\..\jishuqi.map.cdb
.........\..\jishuqi.map.hdb
.........\..\jishuqi.map.logdb
.........\..\jishuqi.map.qmsg
.........\..\jishuqi.pre_map.cdb
.........\..\jishuqi.pre_map.hdb
.........\..\jishuqi.psp
.........\..\jishuqi.rtlv.hdb
.........\..\jishuqi.rtlv_sg.cdb
.........\..\jishuqi.rtlv_sg_swap.cdb
.........\..\jishuqi.sgdiff.cdb
.........\..\jishuqi.sgdiff.hdb
.........\..\jishuqi.signalprobe.cdb
.........\..\jishuqi.sld_design_entry.sci
.........\..\jishuqi.sld_design_entry_dsc.sci
.........\..\jishuqi.smp_dump.txt
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