Description: Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is a local output frequency. The purpose is to extract data from the input clock signal (Q5), their frequency and data rate in line clock rising edge of lock-in data on rising and falling edge PLL.GDF top-level document
- [DPLL.Rar] - digital phase-locked loop PLL design sou
- [pll] - pll.vhd : PLL written in VHDL hardware l
- [DPLL] - DPLL DPLL examples of procedures to help
- [UYYTY] - A high-speed clock extraction on the art
- [PLL] - Phase-locked loop principle Matlab simul
- [gfuzzy] - Based on fuzzy logic control of digital
- [PLL] - Can be achieved automatically PLL functi
- [Phase_Noise] - simulation of PLL loop phase noise
- [PLLfpgapaper] - Paper digital PLL, FPGA implementation f
File list (Check if you may need any files):
Digital phase-locked loop PLL
.............................\dpll.gdf
.............................\edge.gdf
.............................\edge.sym
.............................\fenpin.sym
.............................\fenpin.v
.............................\pll
.............................\...\aa.gdf
.............................\...\edge.acf
.............................\...\edge.fit
.............................\...\edge.gdf
.............................\...\edge.hex
.............................\...\edge.hif
.............................\...\edge.mmf
.............................\...\edge.ndb
.............................\...\edge.pin
.............................\...\edge.pof
.............................\...\edge.rpt
.............................\...\edge.scf
.............................\...\edge.snf
.............................\...\edge.sof
.............................\...\edge.ttf
.............................\...\inst1.gdf
.............................\...\mealy1.acf
.............................\...\mealy1.fit
.............................\...\mealy1.gdf
.............................\...\mealy1.hex
.............................\...\mealy1.hif
.............................\...\mealy1.mmf
.............................\...\mealy1.ndb
.............................\...\mealy1.pin
.............................\...\mealy1.pof
.............................\...\mealy1.rpt
.............................\...\mealy1.scf
.............................\...\mealy1.snf
.............................\...\mealy1.sof
.............................\...\mealy1.ttf
.............................\...\pll.acf
.............................\...\pll.fit
.............................\...\pll.gdf
.............................\...\pll.hif
.............................\...\pll.jam
.............................\...\pll.jbc
.............................\...\pll.mmf
.............................\...\pll.ndb
.............................\...\pll.pin
.............................\...\pll.pof
.............................\...\pll.rpt
.............................\...\pll.scf
.............................\...\pll.snf
.............................\...\pll1.acf
.............................\...\pll1.fit
.............................\...\pll1.gdf
.............................\...\pll1.hif
.............................\...\pll1.jam
.............................\...\pll1.jbc
.............................\...\pll1.mmf
.............................\...\pll1.ndb
.............................\...\pll1.pin
.............................\...\pll1.pof
.............................\...\pll1.rpt
.............................\...\pll1.snf
.............................\read me.txt
.............................\updown_counter.sym
.............................\updown_counter.v
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