Description: FPGA-based arbitrary signal generator, a complete draft graduation project, suitable for students to complete reference
To Search:
- [DDS_Power] - FPGA on the verilog language programming
- [DDSFPGA_cylone] - dds design, spent a week doing, verilog
- [TURSUN] - Is a graduation project please everyone
- [DDS] - So with the DDS-related information and
- [dds] - Based on VHDL+ FPGA design of the DDS si
- [c51shuiwenkongzhi] - danoianji c shui wen kongzhi xitong
- [im] - My graduation project is to document the
- [QuartusIIVHDLDDS] - FPGA-based design of the DDS signal sour
- [pinglvjiFPGA] - Based on the principle of the frequency
- [ISE_11.1_licgen_v2] - This is the method of the new ISE 11 of
File list (Check if you may need any files):
基于FPGA的任意信号发生器.doc