xapp622 644-MHz SDR LVDS Transmitter/Receiver

Title: xapp622

Category:
VHDL-FPGA-Verilog
Tags:
[PDF]
File Size:
347kb
Update:
2012-11-26
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Uploaded by:
wicky

Description: 644-MHz SDR LVDS Transmitter/Receiver

Downloaders recently: [More information of uploader wicky]

To Search: lvds SDR verilog LVDS lvds verilog LVDS receiver xilinx VHDL LVDS Verilog SDR VHDL xapp622 Xili xilinx lvds verilog

[QuartusIIChineseuserguide(Englishtranslatio] - Quartus II Chinese user guide (English v
[lvds_tx_rx_ok] - Nios system
[xapp485] - XILINX company on the flat panel display
[Micron_DDR] - Particles as well as the DDR2 SDRAM init
[Xil3SD1800A_MIG_simplifiedUI_vlog_v92] - verilog achieved spartan 3A dsp start ki
[lvds] - this a LVDS source programme.
[tiaozhifangshidezidongshibie] - Digital signal processing modulation of
[LVDASA] - Principle and Application of LVDS Introd
[featuresofmodulationsignals] - stastical features based modulation reco
[RS232(verilog)] - RS232 serial communication program, incl

File list (Check if you may need any files):

xapp622-06_10_04
................\par_v2p_left
................\............\rx_sdr_16d_4to1_left.edif
................\............\top.edif
................\............\top.ucf
................\............\tx_clocks.edif
................\............\tx_sdr_16d_4to1_left.edif
................\par_v2p_right
................\.............\rx_sdr_16d_4to1_right.edif
................\.............\top.edif
................\.............\top.ucf
................\.............\tx_clocks.edif
................\.............\tx_sdr_16d_4to1_right.edif
................\par_v2p_xlvds
................\.............\rx_sdr_16d_4to1_left.edif
................\.............\top.edif
................\.............\top.ucf
................\.............\trim.ucf
................\.............\tx_clocks.edif
................\.............\tx_sdr_16d_4to1_right.edif
................\.............\xlvds_base.ucf
................\par_v2_left
................\...........\rx_sdr_16d_4to1_left.edif
................\...........\top.edif
................\...........\top.ucf
................\...........\tx_clocks.edif
................\...........\tx_sdr_16d_4to1_left.edif
................\par_v2_right
................\............\rx_sdr_16d_4to1_right.edif
................\............\top.edif
................\............\top.ucf
................\............\tx_clocks.edif
................\............\tx_sdr_16d_4to1_right.edif
................\readme.txt
................\src_vlg
................\.......\rx_sdr_16d_4to1_left.v
................\.......\rx_sdr_16d_4to1_right.v
................\.......\testbench.v
................\.......\top_left.v
................\.......\top_right.v
................\.......\top_xlvds.v
................\.......\tx_clocks.v
................\.......\tx_sdr_16d_4to1_left.v
................\.......\tx_sdr_16d_4to1_right.v
xapp622.pdf

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