Description: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks.
External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets.
The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
- [RISC_Core] - This described in VerilogHDL with an 8-b
- [VHDLpipeline] - Pipeline to achieve the Bible, can great
- [ppc405fx_um] - PowerPC PP405fx all design reference
- [datapath_fifo] - datapath_fifo used in DMA contect PCI in
- [DMA] - DMA Controller Code in VHDL
- [mmarm_EDACN] - The Verilog source code and description
- [Verilog_code_for_AWGN] - verilog code for implementation of awgn
- [RISC] - 32 bit RISC Processor with 3 stage pipel
File list (Check if you may need any files):
Final_Project_Amit_Adoni_&_Tomer_Israel_CPU
...........................................\Do files
...........................................\........\2_words_crc.do
...........................................\........\2_words_crc2.do
...........................................\........\accelerator in the_system.do
...........................................\........\accelerator.do
...........................................\........\branch_logic(1).do
...........................................\........\branch_logic2.do
...........................................\........\cache.do
...........................................\........\cache_comp4.do
...........................................\........\calc_carry.do
...........................................\........\cell.do
...........................................\........\cell_vector.do
...........................................\........\cmos_mux.do
...........................................\........\comparator_1bit.do
...........................................\........\comparator_32bit(1).do
...........................................\........\comparator_4bit(1).do
...........................................\........\control_logic.do
...........................................\........\DFFS_wave.DO
...........................................\........\DFF_wave.do
...........................................\........\FA.do
...........................................\........\first_buffer.do
...........................................\........\first_stage.do
...........................................\........\first_stage_total.do
...........................................\........\hazard_logic.do
...........................................\........\multi_and.do
...........................................\........\multi_inverters.do
...........................................\........\multi_or.do
...........................................\........\multy_cmos_switch_test.do
...........................................\........\mux2(cmos).do
...........................................\........\mux2.do
...........................................\........\mux4.do
...........................................\........\P_G.do
...........................................\........\second_stage.do
...........................................\........\test_all.do
...........................................\........\test_all1.do
...........................................\........\the_system.do
...........................................\........\xor_2.do
...........................................\........\xor_3_input.do
...........................................\........\xor_4.do
...........................................\........\xor_6.do
...........................................\Matlab final project
...........................................\....................\add.m
...........................................\....................\addi.asv
...........................................\....................\addi.m
...........................................\....................\BinEncoder.asv
...........................................\....................\BinEncoder.m
...........................................\....................\BinEncoder1.m
...........................................\....................\bre.m
...........................................\....................\brg.m
...........................................\....................\brl.m
...........................................\....................\bubble_sort.txt
...........................................\....................\checksum.m
...........................................\....................\ConvertToInt.m
...........................................\....................\crc32.m
...........................................\....................\create_test_ram.m
...........................................\....................\culc_crc.asv
...........................................\....................\culc_crc.m
...........................................\....................\flush.m
............
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