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Title: dds Download
 Description: 基于fpga的函数发生器
 Downloaders recently: [More information of uploader 378613779]
  • [DDS_VERILOG] - the cases presented DDS VERIOG procedure
  • [VHDL-Programming-by-Example] - VHDL Programming by Example (McGraw.Hill
  • [Sin_wave] - sin waveform signal from the procedure d
  • [phase] - A low frequency digital phase measuring
  • [dds] - FPGA realization of the use of DDS, sine
  • [dds] - Digital frequency synthesizer. Can gener
  • [DDS] - The design is based on a digital frequen
  • [FPGA-DDS-FM] - DDS signal generator FM Design Principle
File list (Check if you may need any files):
dds
...\db
...\..\add_sub_5lh.tdf
...\..\dds.cbx.xml
...\..\dds.cmp.rdb
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.hif
...\..\dds.map.hdb
...\..\dds.map.qmsg
...\..\dds.sim.qmsg
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\wed.zsf
...\dds.acf
...\dds.asm.rpt
...\dds.done
...\dds.fit.eqn
...\dds.fit.rpt
...\dds.fit.summary
...\dds.flow.rpt
...\dds.hif
...\dds.map.eqn
...\dds.map.rpt
...\dds.map.summary
...\dds.pin
...\dds.qpf
...\dds.qsf
...\dds.qws
...\dds.sim.rpt
...\dds.tan.rpt
...\dds.tan.summary
...\dds.vhd
...\dds.vwf
...\dds_assignment_defaults.qdf
...\lmp_rom.vhd
...\phasesum.vhd
    

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