Description: Verilog language used to describe comparators, data selector
- [veriloghdlQuickStart.Zip] - Verilog HDL Quick Start, which contains
- [Comparators_16B] - Verilog achieve optimization of 16 compa
- [countqi] - Asynchrony preset counter reset the Veri
- [rangewithverilog] - Bubble Sort manner used in Verilog to ac
- [COMP] - Meticulously designed comparator code, a
- [uart16550.tar] - UART16550 controller, verilog
- [RS232] - RS232 serial communication protocol, ver
- [verilog] - Example Collection contains verilog lang
- [DDS] - Our group for a month to do a total of D
- [chh] - Signal generator, can produce a variety
File list (Check if you may need any files):
verilog.doc