Description: EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space. DA external sine wave output function can be realized
- [ddssinegeneratorcode.Rar] - described dds direct digital frequency s
- [dds_8bit] - rom address the width of 8, 256 sine wav
- [eeprom] - EEPROM of the Verilog HDL source code, i
- [phase] - A low frequency digital phase measuring
- [sinwave] - Sine wave signal source, has detailed do
- [EEPROM] - Written in VHDL language IIC achieve EEP
- [VHDL] - DDS have a sine wave (VHDL language) 3MH
- [2fsk-2psk] - CPLD-based digital communications system
File list (Check if you may need any files):
DDS
...\10正弦波数据.txt
...\db
...\..\add_sub_pnh.tdf
...\..\DDS.analyze_file.qmsg
...\..\DDS.asm.qmsg
...\..\DDS.cbx.xml
...\..\DDS.cmp.cdb
...\..\DDS.cmp.hdb
...\..\DDS.cmp.logdb
...\..\DDS.cmp.rdb
...\..\DDS.cmp.tdb
...\..\DDS.cmp0.ddb
...\..\DDS.dbp
...\..\DDS.db_info
...\..\DDS.eco.cdb
...\..\DDS.fit.qmsg
...\..\DDS.fnsim.hdb
...\..\DDS.fnsim.qmsg
...\..\DDS.hier_info
...\..\DDS.hif
...\..\DDS.map.cdb
...\..\DDS.map.hdb
...\..\DDS.map.logdb
...\..\DDS.map.qmsg
...\..\DDS.pre_map.cdb
...\..\DDS.pre_map.hdb
...\..\DDS.psp
...\..\DDS.pss
...\..\DDS.rtlv.hdb
...\..\DDS.rtlv_sg.cdb
...\..\DDS.rtlv_sg_swap.cdb
...\..\DDS.sgdiff.cdb
...\..\DDS.sgdiff.hdb
...\..\DDS.sld_design_entry.sci
...\..\DDS.sld_design_entry_dsc.sci
...\..\DDS.syn_hier_info
...\..\DDS.tan.qmsg
...\..\DDS.tis_db_list.ddb
...\..\mux_efc.tdf
...\..\prev_cmp_DDS.asm.qmsg
...\..\prev_cmp_DDS.fit.qmsg
...\..\prev_cmp_DDS.map.qmsg
...\..\prev_cmp_DDS.qmsg
...\..\prev_cmp_DDS.tan.qmsg
...\..\rom0_ROM_8_58e5cb6.hdl.mif
...\DDS.asm.rpt
...\DDS.bdf
...\DDS.cdf
...\DDS.done
...\DDS.dpf
...\DDS.fit.rpt
...\DDS.fit.summary
...\DDS.flow.rpt
...\DDS.map.rpt
...\DDS.map.smsg
...\DDS.map.summary
...\DDS.pin
...\DDS.pof
...\DDS.qpf
...\DDS.qsf
...\DDS.qws
...\DDS.tan.rpt
...\DDS.tan.summary
...\FENPIN_40.bsf
...\FENPIN_40.v
...\FULLADDER.bsf
...\FULL_ADDER10.v
...\FULL_ADDER10.v.bak
...\F_ADDER.bsf
...\LATCH_10.bsf
...\LATCH_10.v
...\LATCH_10.v.bak
...\ROM_8.bsf
...\ROM_8.v
...\ROM_8.v.bak
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