Description: DDS have a sine wave (VHDL language) 3MHZ generated by the DDS sine wave, VHDL control language
- [dds] - FPGA realization of the use of DDS, sine
- [16] - dds applications arising primarily from
- [sine_testbench] - Sine generator in VHDL.
- [DDS] - Use this procedure to prepare single-chi
- [DDS] - Through the keys produce different wavef
- [ddfs] - Basic FPGA-DDS signal generator, can pro
- [DDS] - EPM7128-based signal generator for digit
- [dds] - Using DDS technology, the use of FPGA ch
File list (Check if you may need any files):
VHDL.txt