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Title: Project4 Download
 Description: This zipfile is composed of a bunch of MIPS codes that might be helpful to some people who are developing CPU
 Downloaders recently: [More information of uploader wanl]
 To Search: MIPS
  • [cpu] - Design of a complete CPU, the FPGA in AL
  • [cpu] - Based on the MIPS instruction set of the
  • [MIPS] - Top level Architecture of MIPS Processor
  • [mips] - mips architrecture i found from the inte
  • [mips] - adgfdhgjjj jdhjhgdkhgjhgjhgkjhgkgkh
  • [mipscpu-source] - mips cpu implementation. MIPS is the wor
File list (Check if you may need any files):
generator
.........\control.conf
.........\EX_to_MEM.conf
.........\gen-latches.rb
.........\gen-pipeline.rb
.........\gen-pipeline.rb~
.........\ID_to_EX.conf
.........\IF_to_ID.conf
.........\Makefile
.........\MEM_to_WB.conf
.........\mips_EXtoMEM.v
.........\mips_IDtoEX.v
.........\PC_to_IF.conf
.........\pipeline.conf
latches
.......\mips_EXtoMEM.v
.......\mips_EX_to_MEM.v
.......\mips_IDtoEX.v
.......\mips_ID_to_EX.v
.......\mips_IF_to_ID.v
.......\mips_MEM_to_WB.v
.......\mips_PC_to_IF.v
.......\mips_Pipeline.v
lib
...\except.v
...\mips_addr_trans.v
...\mips_cache.v
...\mips_defines.v
...\mips_iarbiter.v
...\mips_icache.v
...\mips_mem_sync_cache.v
...\reg.v
...\reg_file.v
...\reg_file_wrapper.v
...\syscall.v
mips447_struct.v
mips_alu.v
mips_control.v
mips_decode.v
mips_execute.v
mips_fetch.v
mips_mem.v
mips_pc.v
mips_scheduler.v
mips_stall.v
mips_writeback.v
test
tester
......\test1.sh
......\test2.sh
......\test3.sh
testjig_core.v
tests
.....\d-read.reg
.....\d-read.s
.....\d-write.reg
.....\d-write.s
.....\i-read.reg
.....\i-read.s
.....\simple_test.s
.....\tester.pl
.....\xecute.reg
.....\xecute.s
.....\xecute.s~
tests2
......\aleph0.reg
......\aleph0.s
......\aleph1.reg
......\aleph1.s
......\betha.reg
......\betha.s
......\gapha0.reg
......\gapha0.s
......\gapha1.reg
......\gapha1.s
......\lbbub0.reg
......\lbbub0.s
......\lbbub1.reg
......\lbbub1.s
......\tester.pl
tests3
......\c0.reg
......\c0.s
......\c1.reg
......\c1.s
......\c2.reg
......\c2.s
......\c3.reg
......\c3.s
......\f0.reg
......\f0.s
......\f1.reg
......\f1.s
......\t0.reg
......\t0.s
......\t1.reg
......\t1.s
......\t2.reg
......\t2.s
......\t3.reg
    

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