Description: spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
- [decdor_38] - VHDL addendum to the encoder, with a var
- [IIS_VHDL] - IIS VHDL interface procedures, the Quart
- [SPI_Code(Verilog)] - SPI bus under the Verilog hardware descr
- [I2SBUS] - I2S Bus Specification
- [USB2.0IP] - Complete Verilog language developed by U
- [i2s_rel1_2] - I2S verilog HDL code including test envi
- [fpdepyou] - hi di attached the matlab source code
- [CAD_Maco] - Use EXCE where to find the location of d
- [SPI] - spi IP based on fpga
- [SPItoI2S] - The file is transferred SPI, I2S Verilog
File list (Check if you may need any files):
spi&i2s3
........\fpga.v
........\i2s.v
........\shiftreg.v
........\spi.v
........\管脚对照表.xls