Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: DDSVerilog Download
 Description: DDS Verilog code. Containing the English documentation
 Downloaders recently: [More information of uploader caixiang0615]
 To Search: DDS Verilog DDSverilog dds fpga verilog verilog DDS dds
  • [ldpc_decoder_802_3an] - 802.3an ldpc code encoding, decoding the
  • [DDS] - DDS debugging experience, VERIOLG the HD
  • [DDS] - DDS principle that there is a timing dia
  • [DDS] - this is a code for DDS in Verilog
  • [dds] - ewfreytrgrwf reggwrter rgterthhrgdfs rgd
  • [FPGA-DDS] - In the FPGA in order to achieve the look
  • [AGA] - Adaptive genetic algorithm generates min
  • [DDS_VERILOG] - verilog dds
File list (Check if you may need any files): 
dds_an_quicklogic.pdf
dds_quicklogic
..............\CLAADD8S.SCH
..............\CLAADD8S.TRE
..............\CLAADD8S.V
..............\CSAC1.SCH
..............\CSAC1.SYM
..............\CSALOWC1.SCH
..............\CSALOWC1.SYM
..............\DDS.V
..............\DDSPA.TF
..............\DDSPM.TF
..............\LOADFW.V
..............\LOADPW.V
..............\PHASEA.V
..............\PHASEMOD.V
..............\PNGEN.V
..............\ROMTAB.V
..............\SINLUP.V

CodeBus www.codebus.net