Description: In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
- [SIN_fashengqi] - 2006altera race-based soft-core Nios wid
- [DDS51] - this program functions : DDS folder proc
- [FPGA--DDS-PhaseMeasure] - Verilog realize the DDS sine wave signal
- [DDS] - FPGA with 51 and realize the process of
- [dds] - FPGA realization of direct digital signa
- [Verilog] - DDS, FPGA generated using Verilog langua
- [AM] - AM modulation works within the FPGA. Wit
- [lfm] - Lmf algorithm on paper, using high-speed
- [DDS] - FPGA to control the AD9854 source file,
File list (Check if you may need any files):
FPGA-DDS .txt