Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: CPU Download
 Description: The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended and provided for simulation.
 Downloaders recently: [More information of uploader 2007zhuwenjuan]
 To Search: CPU VHDL VHDL c VHDL Printer vhdl cpu
  • [cpu-16-vhdl] - 16 cpu vhdl the source code. See for you
  • [CPU] - Using VHDL made easy CPU, to be complete
  • [CPU] - Simple 16-bit CPU design of the VHDL cod
  • [alu] - 4 alu, including computing functionality
  • [RiscCpu] - Verilog-RISC CPU code to achieve a simpl
  • [cpu] - cpu VHDL Design and Implementation of mu
  • [FPGA_DESIGNED] - Have master' s thesis, based on the F
  • [CPU16] - Own use VHDL to write a 16-bit CPU, in s
  • [cpu] - The purpose of this project is to design
  • [CPU] - 32bit pipeline CPU
File list (Check if you may need any files): 
CPU
...\ACC.bsf
...\ACC.vhd
...\ALU.bsf
...\ALU.vhd
...\BR.bsf
...\BR.vhd
...\C.bsf
...\C.vhd
...\change.bsf
...\change.vhd
...\change1.vhd
...\change2.bsf
...\change2.vhd
...\CPU.asm.rpt
...\CPU.bdf
...\CPU.done
...\CPU.fit.rpt
...\CPU.fit.summary
...\CPU.flow.rpt
...\CPU.map.rpt
...\CPU.map.summary
...\CPU.pin
...\CPU.pof
...\CPU.qpf
...\CPU.qsf
...\CPU.qws
...\CPU.sim.rpt
...\CPU.sof
...\CPU.tan.rpt
...\CPU.tan.summary
...\CPU.vwf
...\CPUdesign
...\.........\a.acf
...\.........\a.hif
...\.........\alu.acf
...\.........\alu.fit
...\.........\alu.hex
...\.........\alu.hif
...\.........\alu.mmf
...\.........\alu.ndb
...\.........\alu.pin
...\.........\alu.pof
...\.........\alu.rpt
...\.........\alu.snf
...\.........\alu.sof
...\.........\ALU.sym
...\.........\alu.ttf
...\.........\alu.vhd
...\.........\behind.acf
...\.........\behind.fit
...\.........\behind.hex
...\.........\behind.hif
...\.........\behind.mmf
...\.........\behind.ndb
...\.........\behind.pin
...\.........\behind.pof
...\.........\behind.rpt
...\.........\behind.snf
...\.........\behind.sof
...\.........\BEHIND.sym
...\.........\behind.ttf
...\.........\behind.vhd
...\.........\br.acf
...\.........\br.fit
...\.........\br.hex
...\.........\br.hif
...\.........\br.mmf
...\.........\br.ndb
...\.........\br.pin
...\.........\br.pof
...\.........\br.rpt
...\.........\br.snf
...\.........\br.sof
...\.........\BR.sym
...\.........\br.ttf
...\.........\br.vhd
...\.........\control_unit.acf
...\.........\control_unit.fit
...\.........\control_unit.hex
...\.........\control_unit.hif
...\.........\control_unit.mmf
...\.........\control_unit.ndb
...\.........\control_unit.pin
...\.........\control_unit.pof
...\.........\control_unit.rpt
...\.........\control_unit.snf
...\.........\control_unit.sof
...\.........\CONTROL_UNIT.sym
...\.........\control_unit.ttf
...\.........\control_unit.vhd
...\.........\cpu.acf
...\.........\cpu.fit
...\.........\cpu.gdf
...\.........\cpu.hex
...\.........\cpu.hif
...\.........\cpu.mmf
...\.........\cpu.ndb
...\.........\cpu.pin
...\.........\cpu.pof

CodeBus www.codebus.net