Description: The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions.
At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.
- [alu] - 16-bit RISC CPU
- [CPU] - Using VHDL made easy CPU, to be complete
- [minicpu] - A cpu of the VHDL language program. A ve
- [CPU] - The purpose of this project is to design
- [cpu] - Design of a complete CPU, the FPGA in AL
- [cpu16] - The realization of a 16-bit CPU. Streaml
- [vhdl] - Vhdl classic material, including digital
- [cpudesign_doc] - RISC cpu classic design tutorials, cattl
- [CPU] - Some devices include the preparation of
- [KD-CPU] - Principles of curriculum design to do th
File list (Check if you may need any files):
cpu程序\ALU.bsf
.......\alu.vhd
.......\alu.vhd.bak
.......\BR.bsf
.......\br.vhd
.......\CONTROLUNIT.bsf
.......\controlunit.vhd
.......\controlunit.vhd.bak
.......\cpu.bdf
.......\cpu.done
.......\cpu.fit.smsg
.......\cpu.fit.summary
.......\cpu.map.summary
.......\cpu.pin
.......\cpu.pof
.......\cpu.qpf
.......\cpu.qsf
.......\cpu.sof
.......\cpu.tan.summary
.......\cpu.vwf
.......\IR.bsf
.......\ir.vhd
.......\lpm_ram_dq0.bsf
.......\lpm_ram_dq0.inc
.......\lpm_ram_dq0.vhd
.......\lpm_ram_dq0_wave0.jpg
.......\lpm_ram_dq0_wave1.jpg
.......\lpm_ram_dq0_waveforms.html
.......\lpm_ram_dq1.bsf
.......\lpm_ram_dq1.inc
.......\lpm_ram_dq1.vhd
.......\lpm_ram_dq1_wave0.jpg
.......\lpm_ram_dq1_wave1.jpg
.......\lpm_ram_dq1_waveforms.html
.......\lpm_ram_dq2.bsf
.......\lpm_ram_dq2.inc
.......\lpm_ram_dq2.tdf
.......\lpm_ram_dq2_wave0.jpg
.......\lpm_ram_dq2_wave1.jpg
.......\lpm_ram_dq2_waveforms.html
.......\lpm_ram_dq3.bsf
.......\lpm_ram_dq3.cmp
.......\lpm_ram_dq3.inc
.......\lpm_ram_dq3.vhd
.......\lpm_ram_dq3_inst.vhd
.......\lpm_ram_dq3_wave0.jpg
.......\lpm_ram_dq3_wave1.jpg
.......\lpm_ram_dq3_waveforms.html
.......\lpm_rom0.bsf
.......\lpm_rom0.inc
.......\lpm_rom0.tdf
.......\lpm_rom0_wave0.jpg
.......\lpm_rom0_waveforms.html
.......\lpm_rom1.bsf
.......\lpm_rom1.inc
.......\lpm_rom1.vhd
.......\lpm_rom1_wave0.jpg
.......\lpm_rom1_waveforms.html
.......\MAR.bsf
.......\mar.vhd
.......\MBR.bsf
.......\mbr.vhd
.......\PC.bsf
.......\pc.vhd
.......\ram.mif
.......\rom.mif
.......\rom.vhd
.......\rom.vhd.bak
.......\SHIFT.bsf
.......\shift.vhd
.......\sopc_builder_log.txt
.......\wrom.bsf
.......\wrom.vhd
.......\wrom.vhd.bak
.......\wrom.vwf
.......\db\add_sub_3ph.tdf
.......\..\add_sub_4ph.tdf
.......\..\add_sub_6rh.tdf
.......\..\add_sub_8rh.tdf
.......\..\add_sub_nsh.tdf
.......\..\altsyncram_1q41.tdf
.......\..\altsyncram_41c1.tdf
.......\..\altsyncram_eq21.tdf
.......\..\altsyncram_n0e1.tdf
.......\..\cpu.fit.qmsg
.......\..\cpu.map.bpm
.......\..\cpu.cmp.logdb
.......\..\cpu.cmp.rdb
.......\..\cpu.asm.qmsg
.......\..\cpu.cmp0.ddb
.......\..\prev_cmp_cpu.sim.qmsg
.......\..\cpu.cmp.cdb
.......\..\cpu.psp
.......\..\cpu.dbp
.......\..\cpu.pss
.......\..\cpu0.rtl.mif
.......\..\altsyncram_rqu.tdf
.......\..\cpu.cmp.hdb
.......\..\cpu.tan.qmsg
.......\..\cpu.sld_design_entry.sci
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