Description: Write their own structure on the noc-dimensional mesh network, verilog, accurate simulation results.
- [LM629] - AVR applies to single-chip driver contro
- [Altera] - The use of soft-core processor, Nios Ⅱ t
- [SIMD_Source] - Detect the types of SIMD instructions av
- [dither] - An example of image dithering algorithm,
- [router_routing] - NOC-chip networks realized fpga-based, r
- [router_fifo] - Himself wrote a piece on the network rou
- [FFT1024] - The use of DSP computing 1024-point FFT
- [FPGA_Design_Tutorial(Xilinx)] - Xilinx FPGA Design Tutorial
- [FPGA_note] - This is mainly to learn FPGA design proc
- [4by4] - 4 inputs, 4 outputs, clos network use is
File list (Check if you may need any files):
mesh_dft
........\add2.v
........\crossbar.v
........\crossbar.v.bak
........\inctl.v
........\inctl.v.bak
........\mesh_router.cr.mti
........\mesh_router.mpf
........\msehdft.cr.mti
........\msehdft.mpf
........\router.v
........\router.v.bak
........\sender.v
........\sk.v
........\testbench.v
........\test_inctl.v
........\transcript
........\vish_stacktrace.vstf
........\vsim.wlf
........\work
........\....\@o@p@a
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.vhd
........\....\@s@k
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\@s@s@c
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.vhd
........\....\add2
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\crossbar5x5
........\....\...........\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.vhd
........\....\inctl
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\receive
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\receiver
........\....\........\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\router
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.vhd
........\....\router_dft
........\....\..........\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\sender
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.vhd
........\....\testbench
........\....\.........\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\test_sk
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\tinctl
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.vhd
........\....\_info
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