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VHDL-FPGA-Verilog
Title:
usart
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Category:
VHDL-FPGA-Verilog
Tags:
File Size:
6kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
none
Description:
Usart model in vhdl code
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File list
(Check if you may need any files):
Clock_gen.vhd Rx_async.vhd SCC.vhd Tx_async.vhd
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