Description: And/or parallel series converter input, serial output converter, for example, a 8bit input and/series converter, the output clock frequency is the input clock frequency of 8 times, the arrival of a clock input, 8 input data input port at the same time output to 8 times the speed of 8bit parallel input serial output, as output from a high level or low output, the procedure can be specified.
To Search:
- [A8] - Two processes and string conversion desi
- [parallel_to_serial] - A parallel to serial verilog source code
- [chuan2] - Prepared using verilog HDL and string co
- [bingchuan2] - prepared and verilogHDL string conversio
- [p2s] - And series converter: the input signal i
- [shifter] - Shifter register which can
- [auk_sdsdi] - for FPGA design ,written by Verilog HDL
- [rs232] - Serial 232 program, to achieve and strin
- [p_s] - VHDL language with the realization of an
- [cbzh] - String and convert the verilog file with
File list (Check if you may need any files):
par2ser.txt
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