Description: And series converter: the input signal in parallel to serial output, where attention should be paid to the need to carry out first clock frequency, low-frequency signals received by the control timing is conducive to observation (L lamps can be observed)
To Search:
- [sditest] - Ep3c25 based on the altera sdi ip nuclea
- [1253] - Based on the VHDL language and string co
- [chuan2] - Prepared using verilog HDL and string co
- [bingchuan2] - prepared and verilogHDL string conversio
- [bingchuan] - prepared and verilogHDL string conversio
- [par2ser] - And/or parallel series converter input,
- [p2s] - And the string conversion module, which
- [rs232] - Serial 232 program, to achieve and strin
- [serial_input_parallel_output_module] - serial input parallel output
File list (Check if you may need any files):
p2s
...\div.acf
...\div.fit
...\div.hif
...\div.jam
...\div.jbc
...\div.mmf
...\div.ndb
...\div.pin
...\div.pof
...\div.rpt
...\div.snf
...\DIV.sym
...\div.vhd
...\LIB.DLS
...\p2s.acf
...\p2s.fit
...\p2s.hif
...\p2s.jam
...\p2s.jbc
...\p2s.mmf
...\p2s.ndb
...\p2s.pin
...\p2s.pof
...\p2s.rpt
...\p2s.scf
...\p2s.snf
...\P2S.sym
...\p2s.vhd
...\test.acf
...\test.hif
...\test.mmf
...\top.acf
...\top.fit
...\top.gdf
...\top.hif
...\top.jam
...\top.jbc
...\top.mmf
...\top.ndb
...\top.pin
...\top.pof
...\top.rpt
...\top.scf
...\top.snf
...\U0380056.DLS
...\U0606086.DLS
...\U2863395.DLS
...\U3254565.DLS
...\U5275518.DLS
...\U6246831.DLS
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