Title:
sine_wave_generator_using_FPGA_implementation
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Description: The information on the sine wave generator using FPGA implementation, the principle is the use of built-in rom form, by querying the means to achieve the output, and then an external DAC output frequency of 1MHz
- [tr_wave] - FPGA prepared triangular wave generator,
- [sin] - sin generator can produce sin in VHDL of
- [boxing] - Signal generator by the waveform selecto
File list (Check if you may need any files):
正弦波081220\Chain1.cdf
............\data_rom.bsf
............\data_rom.cmp
............\data_rom.qip
............\data_rom.vhd
............\data_rom_waveforms.html
............\.b\altsyncram_0f71.tdf
............\..\altsyncram_5j82.tdf
............\..\altsyncram_9e91.tdf
............\..\altsyncram_gl71.tdf
............\..\decode_aoi.tdf
............\..\decode_ppa.tdf
............\..\mux_9kb.tdf
............\..\prev_cmp_sin.asm.qmsg
............\..\prev_cmp_sin.fit.qmsg
............\..\prev_cmp_sin.map.qmsg
............\..\prev_cmp_sin.qmsg
............\..\prev_cmp_sin.sim.qmsg
............\..\prev_cmp_sin.tan.qmsg
............\..\sin.asm.qmsg
............\..\sin.asm_labs.ddb
............\..\sin.cbx.xml
............\..\sin.cmp.bpm
............\..\sin.cmp.cdb
............\..\sin.cmp.ecobp
............\..\sin.cmp.hdb
............\..\sin.cmp.logdb
............\..\sin.cmp.rdb
............\..\sin.cmp.tdb
............\..\sin.cmp0.ddb
............\..\sin.cmp2.ddb
............\..\sin.db_info
............\..\sin.eco.cdb
............\..\sin.eds_overflow
............\..\sin.fit.qmsg
............\..\sin.hier_info
............\..\sin.hif
............\..\sin.map.bpm
............\..\sin.map.cdb
............\..\sin.map.ecobp
............\..\sin.map.hdb
............\..\sin.map.logdb
............\..\sin.map.qmsg
............\..\sin.map_bb.cdb
............\..\sin.map_bb.hdb
............\..\sin.map_bb.hdbx
............\..\sin.map_bb.logdb
............\..\sin.pre_map.cdb
............\..\sin.pre_map.hdb
............\..\sin.psp
............\..\sin.root_partition.cmp.atm
............\..\sin.root_partition.cmp.dfp
............\..\sin.root_partition.cmp.hdbx
............\..\sin.root_partition.cmp.logdb
............\..\sin.root_partition.cmp.rcf
............\..\sin.root_partition.map.atm
............\..\sin.root_partition.map.hdbx
............\..\sin.root_partition.map.info
............\..\sin.root_partition.merge_hb.atm
............\..\sin.rtlv.hdb
............\..\sin.rtlv_sg.cdb
............\..\sin.rtlv_sg_swap.cdb
............\..\sin.sgdiff.cdb
............\..\sin.sgdiff.hdb
............\..\sin.signalprobe.cdb
............\..\sin.sim.cvwf
............\..\sin.sim.hdb
............\..\sin.sim.qmsg
............\..\sin.sim.rdb
............\..\sin.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm
............\..\sin.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.dfp
............\..\sin.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.hdbx
............\..\sin.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.logdb
............\..\sin.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
............\..\sin.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx
............\..\sin.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb
............\..\sin.sld_design_entry.sci
............\..\sin.sld_design_entry_dsc.sci
............\..\sin.syn_hier_info
............\..\sin.tan.qmsg
............\..\sin.tis_db_list.ddb
............\..\sin.tmw_info
............\..\wed.wsf
............\EDA综合设计报告.doc
............\EDA综合设计报告.pdf
............\output_file.jic
............\output_file.map
............\sin.asm.rpt
............\sin.done
............\sin.dpf
............\sin.fit.rpt
............\sin.fit.smsg
............\sin.fit.summary
............\sin.flow.rpt
............\sin.jdi
............\sin.map.rpt
............\sin.map.summary
............\sin.mif
............\sin.pin
............\sin.pof
