Description: Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this parameter, the completion of the capacity expansion of RAM. Procedures described in detail
- [ram] - primitive code using VHDL prepared RAM,
- [fifo_VHDL] - FIFO of the source code, a detailed desc
- [vhdlfi] - fifo vhdl source, high reliability, with
- [ram] - a 16 by 4 ram is used for many applicati
- [FIFORAM] - FIFO RAM
- [ADV7180.vhd] - this files describe how to configure an
- [FIFO] - Gives a Gray code using the address codi
- [FIFO] - vhdl code for FIFO memory with controler
- [ad2902] - AD2902 is a kind of ADC chip.it is a fas
File list (Check if you may need any files):
FIFO\fifo_async\compare_addr.v
....\..........\fifo_async.cmd_log
....\..........\fifo_async.ise
....\..........\fifo_async.lso
....\..........\fifo_async.ngc
....\..........\fifo_async.ngr
....\..........\fifo_async.ntrc_log
....\..........\fifo_async.prj
....\..........\fifo_async.restore
....\..........\fifo_async.stx
....\..........\fifo_async.syr
....\..........\fifo_async.v
....\..........\fifo_async.xst
....\..........\fifo_async_summary.html
....\..........\...........xdb\tmp\ise\version
....\..........\..............\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
....\..........\..............\...\...\............\..................\.........\HDProject_StrTbl
....\..........\..............\...\...\............\..................\__stored_object_table__
....\..........\..............\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
....\..........\..............\...\...\............\.........\.......\RunOnce_tcl_StrTbl
....\..........\..............\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
....\..........\..............\...\...\............\................\................\dpm_project_main_StrTbl
....\..........\..............\...\...\............\................\................\NameMap
....\..........\..............\...\...\............\................\................\NameMap_StrTbl
....\..........\..............\...\...\............\................\__stored_objects__
....\..........\..............\...\...\............\................\__stored_objects___StrTbl
....\..........\..............\...\...\............\................\__stored_object_table__
....\..........\..............\...\...\............\................Gui\GuiProjectData
....\..........\..............\...\...\............\...................\GuiProjectData_StrTbl
....\..........\..............\...\...\............\xreport\Gc_RvReportViewer-Current-Module
....\..........\..............\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
....\..........\..............\...\...\............\.......\Gc_RvReportViewer-Module-Data-fifo_async
....\..........\..............\...\...\............\.......\Gc_RvReportViewer-Module-Data-fifo_async_StrTbl
....\..........\..............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
....\..........\..............\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
....\..........\..............\...\...\..REGISTRY__\Autonym\regkeys
....\..........\..............\...\...\............\bitgen\regkeys
....\..........\..............\...\...\............\common\regkeys
....\..........\..............\...\...\............\.pldfit\regkeys
....\..........\..............\...\...\............\dumpngdio\regkeys
....\..........\..............\...\...\............\fuse\regkeys
....\..........\..............\...\...\............\HierarchicalDesign\HDProject\regkeys
....\..........\..............\...\...\............\..................\regkeys
....\..........\..............\...\...\............\hprep6\regkeys
....\..........\..............\...\...\............\idem\regkeys
....\..........\..............\...\...\............\map\regkeys
....\..........\..............\...\...\............\netgen\regkeys
....\..........\..............\...\...\............\.gc2edif\regkeys
....\..........\..............\...\...\............\...build\regkeys
....\..........\..............\...\...\............\..dbuild\regkeys
....\..........\..............\...\...\............\par\regkeys
....\..........\..............\...\...\............\ProjectNavigator\regkeys
....\..........\..............\...\...\............\................Gui\regkeys
....\..........\..............\...\...\............\runner\regkeys
....\..........\..............\...\...\............\SrcCtrl\regkeys
....\..........\..............\...\...\............\.TE\regkeys
....\..........\..............\...\...\............\...\xst\regkeys
....\..........\..............\...\...\............\taengine\regkeys
....\..........\..............\...\...\............\.rce
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