- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 2kb
- Update:
- 2012-11-26
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- 0 Times
- Uploaded by:
- 陈辉
Description: Gives a Gray code using the address coding Yi-step implementation of FIFO method, and gives the VHDL program to address the problems caused by the asynchronous read and write clocks. In order to solve the operational problems of asynchronous FIFO, this paper presents a Gray code to encode the address of the asynchronous FIFO design and circuit design using VHDL language, using Altera' s FPGA realization FLEX10KE series, the circuit software simulation and hardware implementation has passed authentication, and is applied to a variety of circuits. Practice has proved that it can resolve the error generated due to asynchronous, while increasing application flexibility.
- [fifov1] - FIFO (FIFO queue) is usually used for da
- [fifo-1117] - This is the asynchronous FIFO realize th
- [asynchoronization_FIFO_design] - Verilog HDL language programming, Async
- [yibufifo] - Detailed design of asynchronous fifo Gra
- [fifo] - Using VHDL programming asynchronous FIFO
- [75448172geleicounter] - This is the asynchronous fifo realize th
- [FIFO] - 512 × 8bid the FIFO with the project doc
- [fifo] - Asynchronous fifo, to prepare to use Ver
- [verilog_RAM] - verilog implementation of a dual-port RA
- [async-FIFO] - VHDL implementation using asynchronous F
File list (Check if you may need any files):
back_ztj.vhd
yfifo.vhd
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