6clock verilog electronic form. Displays year, mon - CodeBus

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VHDL-FPGA-Verilog

Title: 6clock

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
10kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
phantasm_415

Description: verilog electronic form. Displays year, month, day and support a leap year.

Downloaders recently: [More information of uploader phantasm_415]

To Search: verilog clock

[Verilog_Development_Board_Sources] - friends, I Jawen. previously seen on the
[clock] - Written using Verilog HDL Digital Clock,
[watch] - Using FPGA to achieve with digital watch
[Verilog(clock)] - Verilog language using an electronic bel
[elc_clock] - Verilog design practice elc_clock electr

File list (Check if you may need any files):

6clock\top.v
......\top.v.bak
......\timer0.5m.v.bak
......\timer0.5m.v
......\timerCP.v.bak
......\timer1m.v.bak
......\decode.v.bak
......\decode.v
......\toptimer.v.bak
......\toptimer.v
......\timerCP.v
......\timer2.v.bak
......\timer2.v
6clock

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