Description: With the state machine written in FIR, verilog code, and has passed through simulation
- [two_d_fir] - FIR FILTER Verilog code
- [fir_16] - fir filter-verilog, the fir filter based
- [coeff_rom_0_7] - FIR filter basic verilog code for implem
- [FIR] - FPGA-based FIR filter, including all non
- [beta] - Fir verilog code implemented to find out
- [fir-vhdl-code] - FIR FILTER CODE with VHDL
- [fir] - fir filter, Verilog language written in
- [fir] - Verilog compiled fir filter, input param
- [fir_filter_verilog] - FIR filter verilog project
- [Verilog_Hdl48FIR] - verilog hdl fir
File list (Check if you may need any files):
fir.v