Description: Written by a foreigner HDLC protocols, including documentation, of great reference value
- [rece_7E] - HDLC control began to receive data to th
- [FPGAforDLC] - Using Altera s FPGA chips, in MAX+ Plus
- [hdlc_1] - Advanced Link Control HDLC to send, writ
- [hdlc] - design of HDLC
- [hdlc] - HDLC protocol controller, implemented wi
File list (Check if you may need any files):
LAOWAI
......\CODE
......\....\CVS
......\....\...\Entries
......\....\...\Repository
......\....\...\Root
......\....\...\Template
......\....\LIBS
......\....\....\CVS
......\....\....\...\Entries
......\....\....\...\Repository
......\....\....\...\Root
......\....\....\...\Template
......\....\....\hdlc_components_pkg.vhd
......\....\....\PCK_CRC16_D8.vhd
......\....\MEM_PKG.VHD
......\....\RX
......\....\..\CORE
......\....\..\....\CVS
......\....\..\....\...\Entries
......\....\..\....\...\Repository
......\....\..\....\...\Root
......\....\..\....\...\Template
......\....\..\....\flag_detect.vhd
......\....\..\....\RxChannel.vhd
......\....\..\....\Rxcont.vhd
......\....\..\....\Zero_detect.vhd
......\....\..\CVS
......\....\..\...\Entries
......\....\..\...\Repository
......\....\..\...\Root
......\....\..\...\Template
......\....\..\SCRIPTS
......\....\..\.......\CVS
......\....\..\.......\...\Entries
......\....\..\.......\...\Repository
......\....\..\.......\...\Root
......\....\..\.......\...\Template
......\....\..\.......\WAVE.DO
......\....\..\TB
......\....\..\..\CVS
......\....\..\..\...\Entries
......\....\..\..\...\Repository
......\....\..\..\...\Root
......\....\..\..\...\Template
......\....\..\..\Rx_tb.vhd
......\....\SPMEM.VHD
......\....\tools_pkg.vhd
......\....\TOP
......\....\...\core
......\....\...\....\CVS
......\....\...\....\...\Entries
......\....\...\....\...\Repository
......\....\...\....\...\Root
......\....\...\....\...\Template
......\....\...\....\hdlc.vhd
......\....\...\....\RxBuff.vhd
......\....\...\....\RxFCS.vhd
......\....\...\....\RxSync.vhd
......\....\...\....\TxBuff.vhd
......\....\...\....\TxFCS.vhd
......\....\...\....\TxSync.vhd
......\....\...\....\WB_IF.vhd
......\....\...\CVS
......\....\...\...\Entries
......\....\...\...\Repository
......\....\...\...\Root
......\....\...\...\Template
......\....\...\scripts
......\....\...\.......\CVS
......\....\...\.......\...\Entries
......\....\...\.......\...\Repository
......\....\...\.......\...\Root
......\....\...\.......\...\Template
......\....\...\.......\model
......\....\...\.......\.....\build_hdlc_top.do
......\....\...\.......\.....\build_TxFCS_Buff.do
......\....\...\.......\.....\CVS
......\....\...\.......\.....\...\Entries
......\....\...\.......\.....\...\Repository
......\....\...\.......\.....\...\Root
......\....\...\.......\.....\...\Template
......\....\...\.......\.....\wave.do
......\....\...\.......\nc-sim
......\....\...\.......\......\build_hdlc_top.csh
......\....\...\.......\......\build_RxFCS_Buff.csh
......\....\...\.......\......\build_TxFCS_Buff.csh
......\....\...\.......\......\cds.lib
......\....\...\.......\......\CVS
......\....\...\.......\......\...\Entries
......\....\...\.......\......\...\Repository
......\....\...\.......\......\...\Root
......\....\...\.......\......\...\Template
......\....\...\.......\......\hdl.var
......\....\...\tb
......\....\...\..\CVS
......\....\...\..\...\Entries
......\....\...\..\...\Repository
......\....\...\..\...\Root
......\....\...\..\...\Template
Download