Description: 24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.
To Search:
- [readme_vhd] - SERDES VHDL source code, you can achieve
- [RS232_project] - rs232 verilog project，reciver or trancim
- [FPGA_common_idea] - This article discusses the four commonly
- [p_s] - VHDL language with the realization of an
- [68140323] - vhdl realized and string conversion, and
- [ys] - Two unipolar HDB3-signals HDB3+, and by
File list (Check if you may need any files):
ser_par\par_to_ser24b_fpga1.vhd
.......\Ser_to_Par24b_fpga1.vhd
ser_par
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