Processor_alu this Code is in verilog HDL. This Co

Title: Processor_alu

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
4kb
Update:
2012-11-26
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Uploaded by:
yogeshpatel_ec

Description: this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given

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File list (Check if you may need any files):

Processor_alu
.............\alu_top.v
.............\alu_control_tbw.tfw
.............\IF_alu.v
.............\DC_alu.v
.............\EX_alu.v
.............\alu_control.v

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