Description: Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
- [FPGA_27eg] - FPGA value of the 27 examples. Rar inclu
- [freq] - Based on the quartus2 such as a precisio
- [Freq] - Simple digital frequency meter, using Ve
- [Cymometer] - Home-made square-wave generator and freq
- [onehehe] - Verilog design Cymometer 4, can be measu
- [counter] - Verilog written procedures for counting
- [dispselect] - written in Verilog digital frequency met
- [cymometer] - VerilogHDL languages using digital frequ
- [EPM240_SCH_and_program] - Schematic diagram+ EPM240 cpld procedure
- [cepin] - Frequency meter, in quartus environment
File list (Check if you may need any files):
Cymometer\db\Cymometer.db_info
.........\..\test1.map.qmsg
.........\..\test1.db_info
.........\..\test1.cbx.xml
.........\..\test1.hif
.........\..\test1.cmp.rdb
.........\..\test1.syn_hier_info
.........\..\test1.sld_design_entry.sci
.........\..\test1.psp
.........\..\test1.dbp
.........\..\test1.eco.cdb
.........\..\test1.hier_info
.........\..\test1.rtlv.hdb
.........\..\test1.rtlv_sg_swap.cdb
.........\..\test1.pre_map.hdb
.........\..\test1.pre_map.cdb
.........\..\test1.map.logdb
.........\..\test1.rtlv_sg.cdb
.........\..\test1.sgdiff.hdb
.........\..\test1.fit.qmsg
.........\..\test1.map.cdb
.........\..\test1.map.hdb
.........\..\test1.cmp.logdb
.........\..\test1.sgdiff.cdb
.........\..\test1.sld_design_entry_dsc.sci
.........\..\test1.cmp.kpt
.........\..\Cymometer.eco.cdb
.........\..\test1.cmp.cdb
.........\..\test1.asm.qmsg
.........\..\test1.cmp.hdb
.........\..\test1.asm_labs.ddb
.........\..\test1.tan.qmsg
.........\..\test1.cmp0.ddb
.........\..\test1.cmp.tdb
.........\..\test1.signalprobe.cdb
.........\..\Cymometer.cmp.tdb
.........\..\Cymometer.cmp0.ddb
.........\..\Cymometer.cmp.cdb
.........\..\Cymometer.cbx.xml
.........\..\Cymometer.hif
.........\..\Cymometer.hier_info
.........\..\Cymometer.cmp.hdb
.........\..\Cymometer.signalprobe.cdb
.........\..\Cymometer.cmp.rdb
.........\..\Cymometer.sld_design_entry.sci
.........\..\Cymometer.psp
.........\..\Cymometer.dbp
.........\..\Cymometer.syn_hier_info
.........\..\Cymometer.cmp.kpt
.........\..\Cymometer.map.qmsg
.........\..\Cymometer.rtlv_sg.cdb
.........\..\Cymometer.rtlv.hdb
.........\..\Cymometer.rtlv_sg_swap.cdb
.........\..\Cymometer.pre_map.hdb
.........\..\Cymometer.pre_map.cdb
.........\..\Cymometer.map.logdb
.........\..\Cymometer.sgdiff.cdb
.........\..\Cymometer.sgdiff.hdb
.........\..\Cymometer.sld_design_entry_dsc.sci
.........\..\Cymometer.map.cdb
.........\..\Cymometer.map.hdb
.........\..\Cymometer.fit.qmsg
.........\..\Cymometer.cmp.logdb
.........\..\Cymometer.asm.qmsg
.........\..\Cymometer.asm_labs.ddb
.........\..\Cymometer.tan.qmsg
.........\hardware\default.sch
.........\simulation\speedwave\test1.vho
.........\..........\.........\test1_vhd.sdo
.........\..........\modelsim\test1_modelsim.xrf
.........\..........\........\test1.vo
.........\..........\........\test1_v.sdo
.........\..........\........\modelsim.ini
.........\..........\........\transcript
.........\..........\........\modelsim_work\_info
.........\..........\........\.............\helhdl\_primary.vhd
.........\..........\........\.............\......\_primary.dat
.........\cmp_state.ini
.........\main.v
.........\Cymometer.qpf
.........\Block1.bdf
.........\Cymometer.qws
.........\Cymometer.qsf
.........\Cymometer.map.rpt
.........\Cymometer.map.smsg
.........\Cymometer.flow.rpt
.........\Cymometer.map.summary
.........\Cymometer.fit.rpt
.........\Cymometer.fit.summary
.........\Cymometer.fit.smsg
.........\Cymometer.pof
.........\Cymometer.asm.rpt
.........\Cymometer.tan.summary
.........\Cymometer.tan.rpt
.........\Cymometer.done
.........\Cymometer.dpf
.........\Cymometer.pin
.........\simulation\modelsim\modelsim_work\helhdl
.........\..........\........\.............\_temp
.........\..........\........\modelsim_work
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