Title:
UART_VHDL_Verilog_Lattice
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Description: This compressed package contains serial process VHDL, Verilog, Lattice three versions of the code, have been achieved. In the compressed package, contains very detailed specifications of the serial implementation. Various versions of the code, containing the complete source files, test files, simulation files.
- [uart_vhdl_lattice] - serial port simulated programme of latt
- [UART] - UART serial procedures, verilog statemen
- [RS232_pro] - RS232 verilog coding the entire parametr
- [uart_module] - implement a smart UART interface
- [VXWORKS2] - VXWORKS instances of software developmen
- [simple_pic] - A common interrupt system of the Verilog
- [H6502] - The standard H.264 decoder all verilog s
- [serial] - FPGA-based serial procedures, Verilog la
File list (Check if you may need any files):
uart16550.tar.gz
UART 源码 (lattice version).rar
uart 源码 (Verilog).zip
uart 源码 (VHDL).zip
