Description: 3, the circuit using as little as possible, find two positive integers less than the 100 greatest common divisor and least common multiple. (Not allowed to use mod function), and integrated a circuit simulation
To Search:
- [verilog] - Design of the two athletes running time
- [exer2] - Given a frequency of 33MHz clock, try to
- [exer4] - Design of the two athletes running the s
- [project3] - Design a simple Ethernet test equipment
File list (Check if you may need any files):
exer3\最大公约数\exer3_最大公约数＿report.doc
.....\..........\gcd.v
.....\..........\test_bench.v
.....\..小公倍数\divider.v
.....\..........\gcd.v
.....\..........\min.v
.....\..........\mul8X8.v
.....\..........\test_bench.v
.....\..........\verilog大作业＿最小公倍数＿report.doc
.....\最大公约数
.....\最小公倍数
exer3
.....\要求.doc
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