Description: Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
File list (Check if you may need any files):
UART\db\mytest.asm.qmsg
....\..\mytest.asm_labs.ddb
....\..\mytest.cbx.xml
....\..\mytest.cmp.bpm
....\..\mytest.cmp.cdb
....\..\mytest.cmp.ecobp
....\..\mytest.cmp.hdb
....\..\mytest.cmp.kpt
....\..\mytest.cmp.logdb
....\..\mytest.cmp.rdb
....\..\mytest.cmp_merge.kpt
....\..\mytest.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
....\..\mytest.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
....\..\mytest.db_info
....\..\mytest.eco.cdb
....\..\mytest.eds_overflow
....\..\mytest.fit.qmsg
....\..\mytest.hier_info
....\..\mytest.hif
....\..\mytest.lpc.html
....\..\mytest.lpc.rdb
....\..\mytest.lpc.txt
....\..\mytest.map.bpm
....\..\mytest.map.cdb
....\..\mytest.map.ecobp
....\..\mytest.map.hdb
....\..\mytest.map.kpt
....\..\mytest.map.logdb
....\..\mytest.map.qmsg
....\..\mytest.map_bb.cdb
....\..\mytest.map_bb.hdb
....\..\mytest.map_bb.logdb
....\..\mytest.pre_map.cdb
....\..\mytest.pre_map.hdb
....\..\mytest.rtlv.hdb
....\..\mytest.rtlv_sg.cdb
....\..\mytest.rtlv_sg_swap.cdb
....\..\mytest.sgdiff.cdb
....\..\mytest.sgdiff.hdb
....\..\mytest.sim.cvwf
....\..\mytest.sim.hdb
....\..\mytest.sim.qmsg
....\..\mytest.sim.rdb
....\..\mytest.sld_design_entry.sci
....\..\mytest.sld_design_entry_dsc.sci
....\..\mytest.sta.qmsg
....\..\mytest.sta.rdb
....\..\mytest.sta_cmp.8_slow_1200mv_85c.tdb
....\..\mytest.syn_hier_info
....\..\mytest.tiscmp.fast_1200mv_0c.ddb
....\..\mytest.tiscmp.slow_1200mv_0c.ddb
....\..\mytest.tiscmp.slow_1200mv_85c.ddb
....\..\mytest.tis_db_list.ddb
....\..\mytest.tmw_info
....\..\prev_cmp_mytest.asm.qmsg
....\..\prev_cmp_mytest.fit.qmsg
....\..\prev_cmp_mytest.map.qmsg
....\..\prev_cmp_mytest.qmsg
....\..\prev_cmp_mytest.sim.qmsg
....\..\prev_cmp_mytest.sta.qmsg
....\..\wed.wsf
....\incremental_db\compiled_partitions\mytest.root_partition.cmp.atm
....\..............\...................\mytest.root_partition.cmp.dfp
....\..............\...................\mytest.root_partition.cmp.hdbx
....\..............\...................\mytest.root_partition.cmp.kpt
....\..............\...................\mytest.root_partition.cmp.logdb
....\..............\...................\mytest.root_partition.cmp.rcf
....\..............\...................\mytest.root_partition.map.atm
....\..............\...................\mytest.root_partition.map.dpi
....\..............\...................\mytest.root_partition.map.hdbx
....\..............\...................\mytest.root_partition.map.kpt
....\..............\README
....\mytest.asm.rpt
....\mytest.done
....\mytest.fit.rpt
....\mytest.fit.smsg
....\mytest.fit.summary
....\mytest.flow.rpt
....\mytest.map.rpt
....\mytest.map.smsg
....\mytest.map.summary
....\mytest.pin
....\mytest.qpf
....\mytest.qsf
....\mytest.qws
....\mytest.sim.rpt
....\mytest.sof
....\mytest.sta.rpt
....\mytest.sta.summary
....\mytest.v
....\mytest.v.bak
....\mytest.vwf
....\UART.vhd
....\URAT.v
....\incremental_db\compiled_partitions
....\db
....\incremental_db
UART
Download