USB2.0-IP-core Written by verilog USB2.0, includin

Title: USB2.0-IP-core

Category:
VHDL-FPGA-Verilog
Tags:
[PDF]
File Size:
196kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
lyx63s

Description: Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help

Downloaders recently: [More information of uploader lyx63s]

To Search:

[IPcore] - A very useful IP core resources, which i
[usbtrace[1].v1.1] - usb2.0 trace verilog code very useful
[RS232-RefComp] - Very useful on serial vhdl language prog
[barcodescanner] - Operating systems in the iphone bar code
[u-boot-1.2.0] - uboot1.2.0 complete source code for the
[ps2] - Fpga based on the ps2 keyboard interface
[USB_SLAVE_700AN_RD] - USB2.0 syn FIFO read

File list (Check if you may need any files):

USB2.0 IP核\usb_funct\bench\CVS\Entries
...........\.........\.....\...\Repository
...........\.........\.....\...\Root
...........\.........\.....\verilog\CVS\Entries
...........\.........\.....\.......\...\Repository
...........\.........\.....\.......\...\Root
...........\.........\doc\CVS\Entries
...........\.........\...\...\Repository
...........\.........\...\...\Root
...........\.........\...\README.txt
...........\.........\...\STATUS.txt
...........\.........\...\usb_doc.pdf
...........\.........\rtl\CVS\Entries
...........\.........\...\...\Repository
...........\.........\...\...\Root
...........\.........\...\verilog\CVS\Entries
...........\.........\...\.......\...\Repository
...........\.........\...\.......\...\Root
...........\.........\...\.......\usbf_crc16.v
...........\.........\...\.......\usbf_crc5.v
...........\.........\...\.......\usbf_defines.v
...........\.........\...\.......\usbf_ep_rf.v
...........\.........\...\.......\usbf_ep_rf_dummy.v
...........\.........\...\.......\usbf_idma.v
...........\.........\...\.......\usbf_mem_arb.v
...........\.........\...\.......\usbf_pa.v
...........\.........\...\.......\usbf_pd.v
...........\.........\...\.......\usbf_pe.v
...........\.........\...\.......\usbf_pl.v
...........\.........\...\.......\usbf_rf.v
...........\.........\...\.......\usbf_top.v
...........\.........\...\.......\usbf_utmi_if.v
...........\.........\...\.......\usbf_utmi_ls.v
...........\.........\...\.......\usbf_wb.v
...........\.........\sim\CVS\Entries
...........\.........\...\...\Repository
...........\.........\...\...\Root
...........\.........\...\rtl_sim\bin\CVS\Entries
...........\.........\...\.......\...\...\Repository
...........\.........\...\.......\...\...\Root
...........\.........\...\.......\CVS\Entries
...........\.........\...\.......\...\Repository
...........\.........\...\.......\...\Root
...........\.........\...\.......\run\CVS\Entries
...........\.........\...\.......\...\...\Repository
...........\.........\...\.......\...\...\Root
...........\.........\.yn\bin\comp.dc
...........\.........\...\...\CVS\Entries
...........\.........\...\...\...\Repository
...........\.........\...\...\...\Root
...........\.........\...\...\design_spec.dc
...........\.........\...\...\lib_spec.dc
...........\.........\...\...\read.dc
...........\.........\...\CVS\Entries
...........\.........\...\...\Repository
...........\.........\...\...\Root
...........\.........\...\log\CVS\Entries
...........\.........\...\...\...\Repository
...........\.........\...\...\...\Root
...........\.........\...\out\CVS\Entries
...........\.........\...\...\...\Repository
...........\.........\...\...\...\Root
...........\.........\...\run\CVS\Entries
...........\.........\...\...\...\Repository
...........\.........\...\...\...\Root
...........\.........\.im\rtl_sim\bin\CVS
...........\.........\...\.......\run\CVS
...........\.........\bench\verilog\CVS
...........\.........\rtl\verilog\CVS
...........\.........\sim\rtl_sim\bin
...........\.........\...\.......\CVS
...........\.........\...\.......\run
...........\.........\.yn\bin\CVS
...........\.........\...\log\CVS
...........\.........\...\out\CVS
...........\.........\...\run\CVS
...........\.........\bench\CVS
...........\.........\.....\verilog
...........\.........\doc\CVS
...........\.........\rtl\CVS
...........\.........\...\verilog
...........\.........\sim\CVS
...........\.........\...\rtl_sim
...........\.........\.yn\bin
...........\.........\...\CVS
...........\.........\...\log
...........\.........\...\out
...........\.........\...\run
...........\.........\bench
...........\.........\doc
...........\.........\rtl
...........\.........\sim
...........\.........\syn
...........\usb_funct
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