Description: This procedure achieved PCM30 frame synchronization and detection step, using verilog programming, includes the project file.
- [pci-verilog] - USB and PCI bus design some of the sourc
- [uart_0910] - uart serial transmission verilog RTL-lev
File list (Check if you may need any files):
PCM30_Frame_Sync\PCM30.v
................\PCM30_Frame_Sync.cr.mti
................\PCM30_Frame_Sync.mpf
................\PCM30_Frame_Sync.v
................\PCM30_Frame_Sync1.v
................\PCM30_test.v
................\PCM30_wu.v
................\PCM_test.v
................\vsim.wlf
................\work\_info
................\....\@p@c@m_test\verilog.asm
................\....\...........\_primary.dat
................\....\...........\_primary.vhd
................\....\......30_@frame_@sync\verilog.asm
................\....\.....................\_primary.dat
................\....\.....................\_primary.vhd
................\....\_temp
................\....\@p@c@m_test
................\....\@p@c@m30_@frame_@sync
................\work
PCM30_Frame_Sync
Download