File list (Check if you may need any files):
AES高级加密算法的verilog语言实现\aes_core\bench\CVS\Entries
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................................\........\.....\verilog\CVS\Entries
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................................\........\.....\.......\test_bench_top.v
................................\........\CVS\Entries
................................\........\...\Repository
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................................\........\doc\aes.pdf
................................\........\...\CVS\Entries
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................................\........\rtl\CVS\Entries
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................................\........\...\verilog\aes_cipher_top.v
................................\........\...\.......\aes_inv_cipher_top.v
................................\........\...\.......\aes_inv_sbox.v
................................\........\...\.......\aes_key_expand_128.v
................................\........\...\.......\aes_rcon.v
................................\........\...\.......\aes_sbox.v
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................................\........\...\.......\timescale.v
................................\........\sim\CVS\Entries
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................................\........\...\rtl_sim\bin\CVS\Entries
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................................\........\...\.......\...\Makefile
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................................\........\...\.......\run\CVS\Entries
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................................\........\...\.......\...\waves\CVS\Entries
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................................\........\...\.......\...\.....\waves.do
................................\........\.yn\bin\comp.dc
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................................\........\...\...\design_spec.dc
................................\........\...\...\lib_spec.dc
................................\........\...\...\read.dc
................................\........\...\CVS\Entries
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................................\........\vim_session.vim
................................\........\sim\rtl_sim\run\waves\CVS
................................\........\...\.......\bin\CVS
................................\........\...\.......\run\CVS
................................\........\...\.......\...\waves
................................\........\bench\verilog\CVS
................................\........\rtl\verilog\CVS
................................\........\sim\rtl_sim\bin
................................\........\...\.......\CVS
................................\........\...\.......\run
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