Description: Based on ISE' s Kam-frequency phase detector, development board: xilinx company spartan 3E 500. Precision 1hz, 1 degree. Entirely correct.
To Search:
- [digitalPLL] - DPLL realize source, has a great referen
- [E1_DCR] - 2MHz data clock recovery circuit, includ
- [PD_using_FPGA] - Verilog preparation phase of the FPGA-ba
- [xloader.tar] - This is TI' s OMAP3530 The X-loader s
- [WMP_RMVB_PLUGIN] - WINDOWS CE platform, the RMVB decoder pl
- [AESverilog] - AES encryption algorithm in Verilog Impl
File list (Check if you may need any files):
jianxiang\mymodel\model\bitgen.xmsgs
.........\.......\.....\ChipS_1.cdc
.........\.......\.....\clk7seg.vhd
.........\.......\.....\clk7seg_wrapper.ngc
.........\.......\.....\clock_generator_0_wrapper.ngc
.........\.......\.....\device_usage_statistics.html
.........\.......\.....\dlmb_cntlr_wrapper.ngc
.........\.......\.....\dlmb_wrapper.ngc
.........\.......\.....\edkBmmFile.bmm
.........\.......\.....\edkBmmFile_bd.bmm
.........\.......\.....\ilmb_cntlr_wrapper.ngc
.........\.......\.....\ilmb_wrapper.ngc
.........\.......\.....\in_first_wrapper.ngc
.........\.......\.....\in_second_wrapper.ngc
.........\.......\.....\in_third_wrapper.ngc
.........\.......\.....\jiping.v
.........\.......\.....\jiping.vhd
.........\.......\.....\leds_8bit_wrapper.ngc
.........\.......\.....\lmb_bram_wrapper.ngc
.........\.......\.....\map.xmsgs
.........\.......\.....\mb_plb_wrapper.ngc
.........\.......\.....\mdm_0_wrapper.ngc
.........\.......\.....\.icroblaze\blockdiagram\.dswkshop\MdtSvgBLKD_Dimensions.xsl
.........\.......\.....\..........\............\.........\MdtSvgDiag_Colors.xsl
.........\.......\.....\..........\............\.........\MdtSvgDiag_Globals.xsl
.........\.......\.....\..........\............\.........\MdtSvgDiag_StyleDefs.css
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_BusLaneSpaces.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_Busses.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_Functions.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_Globals.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_IOPorts.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_Main.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_Peripherals.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_Processors.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgBLKD_StyleDefs.xsl
.........\.......\.....\..........\............\.........\MdtTinySvgDiag_BifShapes.xsl
.........\.......\.....\..........\............\.........\MdtXdsGen_Colors.xsl
.........\.......\.....\..........\............\.........\MdtXdsGen_Globals.xsl
.........\.......\.....\..........\............\.........\MdtXdsGen_HTMLDatasheet.css
.........\.......\.....\..........\............\.........\MdtXdsGen_HTMLDatasheet.xsl
.........\.......\.....\..........\............\.........\MdtXdsGen_HTMLIPSection.xsl
.........\.......\.....\..........\............\.........\MdtXdsGen_HTMLMemoryMap.xsl
.........\.......\.....\..........\............\.........\MdtXdsGen_HTMLTOCTree.xsl
.........\.......\.....\..........\............\.........\microblaze_w_blkd.xml
.........\.......\.....\..........\............\.........\svg10.dtd
.........\.......\.....\..........\............\microblaze.css
.........\.......\.....\..........\............\microblaze.svg
.........\.......\.....\..........\............\svg10.dtd
.........\.......\.....\..........\clock_generator_0.log
.........\.......\.....\..........\data\microblaze.ucf
.........\.......\.....\..........\etc\bitgen.ut
.........\.......\.....\..........\...\bitgen.ut.virtex5
.........\.......\.....\..........\...\download.cmd
.........\.......\.....\..........\...\fast_runtime.opt
.........\.......\.....\..........\...\fast_runtime.opt.virtex5
.........\.......\.....\..........\hdl\clk7seg_wrapper.vhd
.........\.......\.....\..........\...\clock_generator_0_wrapper.vhd
.........\.......\.....\..........\...\dlmb_cntlr_wrapper.vhd
.........\.......\.....\..........\...\dlmb_wrapper.vhd
.........\.......\.....\..........\...\elaborate\lmb_bram_elaborate_v1_00_a\hdl\vhdl\lmb_bram_elaborate.vhd
.........\.......\.....\..........\...\ilmb_cntlr_wrapper.vhd
.........\.......\.....\..........\...\ilmb_wrapper.vhd
.........\.......\.....\..........\...\in_first_wrapper.vhd
.........\.......\.....\..........\...\in_second_wrapper.vhd
.........\.......\.....\..........\...\in_third_wrapper.vhd
.........\
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