Description: The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language!
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To Search:
- [verilog_delta_complete] - Verilog designs sawtooth waveform module
- [QIMO] - Verilog prepared arbitrary waveform gene
- [DDS] - Quartus on the DDS, can occur sine wave,
- [FINALWORK] - Simple signal generator can produce sine
- [1212] - VERILOG+ HDL hardware description langua
- [dds] - Under the DDS in quartus design, Verilog
- [Core8051] - VERILOG Core8051 written test routines,
File list (Check if you may need any files):
DDS信号发生器\one_key.v
.............\DDS.v
.............\DDS_1.qpf
.............\DDS_1.qsf
.............\DDS_1.map.smsg
.............\DDS_1.map.summary
.............\DDS_1.done
.............\DDS.bsf
.............\DDS_tu.bdf
.............\one_key.bsf
.............\sine.bsf
.............\triangle.hex
.............\juxingbo.bsf
.............\pll.v
.............\pll.ppf
.............\pll.bsf
.............\pll_bb.v
.............\pll.qip
.............\DDS_sine.hex
.............\juchibo.bsf
.............\juchibo.v
.............\juchibo.qip
.............\DDS_LJ.stp
.............\rectangle.hex
.............\DDS_1.dpf
.............\sanjiaobo.bsf
.............\sanjiaobo.v
.............\DDS_1.jdi
.............\rectangle.bsf
.............\serration.hex
.............\juxingbo.v
.............\rectangle.v
.............\rectangle_bb.v
.............\rectangle.qip
.............\DDS_1.qws
.............\serration.bsf
.............\zhenxianbo.bsf
.............\juxingbo_bb.v
.............\serration_bb.v
.............\serration.qip
.............\sanjiaobo_bb.v
.............\sanjiaobo.qip
.............\juxingbo.qip
.............\juchibo_bb.v
.............\zhenxianbo.v
.............\zhenxianbo_bb.v
.............\zhenxianbo.qip
.............\DDS_1.pin
.............\DDS_1.fit.smsg
.............\DDS_1.fit.summary
.............\DDS_1.sof
.............\DDS_1.pof
.............\DDS_1.tan.summary
.............\triangle.v
.............\triangle_bb.v
DDS信号发生器
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