Verilog_CY7C68013-SLAVE-FIFO Prepared with the VER

Title: Verilog_CY7C68013-SLAVE-FIFO

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VHDL-FPGA-Verilog
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2012-11-26
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Description: Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven

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To Search: CY7C68013 slave fifo CY7C68013 slave FIFO slavefifo driv CY7C68013 slave

[RayTracingCode] - Ray Tracing (ray tracing) algorithm to a
[EZ_USB_cy7c68013_driver] - usb drivers, using vc, ddk development.
[HighSpeedAD] - FPGA
[ez_usb_fx2_gpif_primer_design_files] - CY7C68013 with two examples of the devel
[68013FIFOIN] - Verilog HDL prepared CY7C68013 SLAVE FIF
[cy7c68013] - Mainly about the firmware on the cy7c680
[cy7c68013] - Usb firmware code development, to achiev
[USB_Interface] - verilog USB
[FX2-Slave-FIFO] - The most common USB data acquisition sys

File list (Check if you may need any files):

Verilog CY7C68013 SLAVE FIFO\使用说明请参看右侧注释====〉〉.txt
............................\同步FIFOIN测试通过\README.txt
............................\..................\同步AUTOIN测试说明.pdf
............................\..................\....自动输入CPLD\db\fifo_cntl.cbx.xml
............................\..................\................\..\fifo_cntl.cmp.rdb
............................\..................\................\..\fifo_cntl.db_info
............................\..................\................\..\fifo_cntl.eco.cdb
............................\..................\................\..\fifo_cntl.hier_info
............................\..................\................\..\fifo_cntl.hif
............................\..................\................\..\fifo_cntl.map.hdb
............................\..................\................\..\fifo_cntl.map.qmsg
............................\..................\................\..\fifo_cntl.pre_map.cdb
............................\..................\................\..\fifo_cntl.pre_map.hdb
............................\..................\................\..\fifo_cntl.rtlv.hdb
............................\..................\................\..\fifo_cntl.rtlv_sg.cdb
............................\..................\................\..\fifo_cntl.rtlv_sg_swap.cdb
............................\..................\................\..\fifo_cntl.sim_ori.vwf
............................\..................\................\..\fifo_cntl.sld_design_entry.sci
............................\..................\................\..\fifo_cntl.sld_design_entry_dsc.sci
............................\..................\................\..\fifo_cntl.tis_db_list.ddb
............................\..................\................\..\prev_cmp_fifo_cntl.asm.qmsg
............................\..................\................\..\prev_cmp_fifo_cntl.fit.qmsg
............................\..................\................\..\prev_cmp_fifo_cntl.map.qmsg
............................\..................\................\..\prev_cmp_fifo_cntl.qmsg
............................\..................\................\..\prev_cmp_fifo_cntl.sim.qmsg
............................\..................\................\..\prev_cmp_fifo_cntl.tan.qmsg
............................\..................\................\..\wed.wsf
............................\..................\................\fifo_cntl.asm.rpt
............................\..................\................\fifo_cntl.cdf
............................\..................\................\fifo_cntl.done
............................\..................\................\fifo_cntl.dpf
............................\..................\................\fifo_cntl.fit.rpt
............................\..................\................\fifo_cntl.fit.smsg
............................\..................\................\fifo_cntl.fit.summary
............................\..................\................\fifo_cntl.flow.rpt
............................\..................\................\fifo_cntl.map.rpt
............................\..................\................\fifo_cntl.map.smsg
............................\..................\................\fifo_cntl.map.summary
............................\..................\................\fifo_cntl.pin
............................\..................\................\fifo_cntl.pof
............................\..................\................\fifo_cntl.qpf
............................\..................\................\fifo_cntl.qsf
............................\..................\................\fifo_cntl.qws
............................\..................\................\fifo_cntl.sim.rpt
............................\..................\................\fifo_cntl.tan.rpt
............................\..................\................\fifo_cntl.tan.summary
............................\..................\................\fifo_cntl.v
............................\..................\................\fifo_cntl.vwf
............

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