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[Other resource] 数字锁相环设计源程序 DL : 2: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Date : 2008-10-13 Size : 118.55kb User : 杰轩
[Other resource] 数字锁相环dll_code DL : 1: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
Date : 2008-10-13 Size : 119.9kb User : zlin
[Develop Tools] 复件数字锁相环程序 DL : 1: 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Date : 2008-10-13 Size : 118.3kb User : zhangfj_99
[Other resource] 数字锁相环 DL : 1: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Date : 2008-10-13 Size : 122.26kb User : 于洪彪
[SourceCode] verilog dpll（数字锁相环） DL : 0: 用xilinx ise 10.1实现了数字锁相环，仅供参考
Date : 2011-04-21 Size : 651.94kb User : ronglijun@gmail.com
[SourceCode] verilog全数字锁相环pll DL : 0: verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
Date : 2011-05-27 Size : 374.68kb User : sakajj
[Driver Develop] 全数字锁相环 DL : 1: 详细介绍数字锁相环的工程
Date : 2011-09-17 Size : 119.64kb User : hyl66313@163.com
[VHDL-FPGA-Verilog] 数字锁相环 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Date : 2025-07-01 Size : 122kb User : 于洪彪
[VHDL-FPGA-Verilog] pll DL : 1: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
Date : 2025-07-01 Size : 109kb User : 孙犁
[VHDL-FPGA-Verilog] 数字锁相环设计源程序 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Date : 2025-07-01 Size : 118kb User : 杰轩
[Post-TeleCom sofeware systems] 数字锁相环dll_code DL : 0: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
Date : 2025-07-01 Size : 120kb User : zlin
[matlab] DPLL DL : 1: 数字锁相环DPLL实例程序，帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
Date : 2025-07-01 Size : 1kb User : 李向坤
[Books] 复件数字锁相环程序 DL : 0: 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Date : 2025-07-01 Size : 118kb User :
[Other] 基于FPGA的全数字锁相环设计 DL : 1: 用vhdl编写的基于fpga的数字频率计程序算法-prepared using VHDL they simply based on the number of procedures Cymometer Algorithm
Date : 2025-07-01 Size : 280kb User : 黄开通
[Communication] dpll_4 DL : 0: 实现4阶数字锁相环，老外写的，有详细注释，如果您觉得不错，就re一下-achieve four bands DPLL, a foreigner writing a detailed notes, if you think it's good, what re
Date : 2025-07-01 Size : 2kb User : liu
[Other Embeded program] verilogpll DL : 0: 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
Date : 2025-07-01 Size : 3kb User : letheo
[Software Engineering] PLLprogram DL : 0: 数字锁相环程序，适合于FM、AM开发数字锁相环程序，适合于FM、AM开发-DPLL procedures for FM, AM Development DPLL procedures for FM, AM Development
Date : 2025-07-01 Size : 30kb User : whuasan
[OS Develop] PLLpro DL : 0: 关于数字锁相环的使用，结合FM,AM的使用来说明-DPLL on the use of combined FM and AM to illustrate the use of
Date : 2025-07-01 Size : 10kb User : whuayan
[Software Engineering] 010919.pdf DL : 0: 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL description and achieve functional simulation, followed by graphic shows
Date : 2025-07-01 Size : 280kb User : 巢海步
[Communication-Mobile] pll_improvement DL : 0: 一种改进的全数字锁相环设计一种改进的全数字锁相环设计-an improved DPLL design an improved design DPLL
Date : 2025-07-01 Size : 100kb User : 李敏

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