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[SourceCode] verilog全数字锁相环pll

Description: verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
Platform: | Size: 383668 | Author: sakajj | Hits:

[Books] 锁相环技术

Description: 国外经典教材锁相环技术
Platform: | Size: 2193651 | Author: hezheng820@sina.com | Hits:

[VHDL-FPGA-Verilog] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 120832 | Author: 杰轩 | Hits:

[Post-TeleCom sofeware systems] 数字锁相环dll_code

Description: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
Platform: | Size: 122880 | Author: zlin | Hits:

[Books] 复件 数字锁相环程序

Description: 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Platform: | Size: 120832 | Author: | Hits:

[Communication] dpll_4

Description: 实现4阶数字锁相环，老外写的，有详细注释，如果您觉得不错，就re一下-achieve four bands DPLL, a foreigner writing a detailed notes, if you think it's good, what re
Platform: | Size: 2048 | Author: liu | Hits:

[GPS develop] c6_PLLsim

Description: 这个程序是matlab用来来对锁相环（PLL）进行仿真的，这样的选择基于多方面的考虑-This procedure is used Matlab to the phase-locked loop (PLL) simulation, This choice is based on a number of considerations
Platform: | Size: 1024 | Author: lizhihui | Hits:

[Embeded-SCM Develop] pll

Description: 该程序实现的锁相环，运行环境为matlab，二阶的环路滤波器-The program realization of phase-locked loop, operating environment for matlab, the second-order loop filter
Platform: | Size: 1024 | Author: change | Hits:

[Software Engineering] PLL

Description: 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！-Abroad, a good digital phase-locked loop (PLL) design documents (after extracting PLL.pdf), can not look at Yo!
Platform: | Size: 352256 | Author: | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
Platform: | Size: 178176 | Author: 冯勇 | Hits:

[VHDL-FPGA-Verilog] myDPll

Description: 本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book
Platform: | Size: 1024 | Author: 杨广 | Hits:

[Communication-Mobile] pll

Description: 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
Platform: | Size: 111616 | Author: qin | Hits:

[SCM] chenggong1204

Description: 用单片机控制锁相环，倍频数由外设键盘输入，输了频率范围0.1KHZ到80KHZ-89C51+PLL
Platform: | Size: 2048 | Author: wangbing | Hits:

[Communication-Mobile] PLL

Description: 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
Platform: | Size: 1024 | Author: wangxinyi | Hits:

[matlab] pll

Description: 设计的软件锁相环的例子，自己写的，根据原理编的-PLL design example of software that he wrote, according to the principle for the
Platform: | Size: 2048 | Author: zhouxiaoshu | Hits:

[matlab] PLL

Description: 利用锁相环，比较好的实现了载波同步-PLL
Platform: | Size: 9216 | Author: xiaobo | Hits:

[matlab] pll

Description: 用matlab模拟仿真锁相环，一个很好的程序，希望能帮到你-PLL with matlab simulation, a very good program, hope you can help
Platform: | Size: 1024 | Author: 偶轩昂亲 | Hits:

[DSP program] 并网逆变器的程序电流环控制并有DA以及锁相部分

Description: 光伏逆变锁相环，使用DSP28335，实现频率跟踪，首先采样，然后PI，然后输出(Photovoltaic inverter PLL, using DSP28335, to achieve frequency tracking, first sampling, then PI, and then output)
Platform: | Size: 882688 | Author: 豆豆1233321 | Hits:

[Other] 并网逆变器中全软件锁相环的设计与实现

Description: 讲述并网逆变器中全软件锁相环的设计与实现，，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）(and implementation of all software phase-locked loop in grid connected inverter is described, that is, detecting the positive and negative component of the fundamental wave under unbalanced grid voltage conditions. Explicitly, a positive decoupling phase locked loop (double DQ - PLL) based on a new sequence detector dual synchronous coordinate system (double DQ - PLL) is proposed, which completely eliminates the traditional synchronous reference frame (SRF - PLL PLL) for detection error.)
Platform: | Size: 4512768 | Author: 醚 | Hits:

[Embeded-SCM Develop] PLL（锁相环）_TEST_OK

Description: 通过STM32程序的编写来形成闭环锁相环，锁住波形的稳定，保持系统的稳定。(Through the preparation of STM32 program to form a closed-loop phase-locked loop, lock waveform stability, maintain the stability of the system)
Platform: | Size: 37888 | Author: wuil- | Hits:
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