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[Other] ahb_interface

Description: AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
Platform: | Size: 540672 | Author: Bill Guan | Hits:

[Documents] amba

Description: doc file on AMBA...advanced microcontroller bus architecture ...basic og amba ahb, asb, apb
Platform: | Size: 289792 | Author: ashish | Hits:

[VHDL-FPGA-Verilog] CODE

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram verilog
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA_V2.0_CN

Description: ARM公司高级微控制器总线体系（Advanced Microcontroller Bus Architecture AMBA ）规范中文版，包括ASB，AHB，APB总线-Senior ARM microcontroller bus system (Advanced Microcontroller Bus Architecture AMBA) specification, including the ASB, AHB, APB bus
Platform: | Size: 1077248 | Author: 陶戈丹 | Hits:

[VHDL-FPGA-Verilog] masterdecoder

Description: AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[VHDL-FPGA-Verilog] ahb_system_generator_latest.tar

Description: this project relates ahb
Platform: | Size: 268288 | Author: david | Hits:

[Software Engineering] IHI0011A_AMBA_SPEC

Description: AMBA2.0规范. 研究和开发AHB总线相关的ASIC工程师可以参考-AMBA2.0 specifications. AHB bus-related research and development engineers can refer to the ASIC
Platform: | Size: 888832 | Author: jx.liang | Hits:

[VHDL-FPGA-Verilog] AHB_SRRAM

Description: SSRAM with AHB bus interface source code
Platform: | Size: 205824 | Author: nan | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
Platform: | Size: 198656 | Author: guoxiaojin | Hits:

[VHDL-FPGA-Verilog] slaveAHB

Description: amba总线的AHB部分，与从机相连接口的写法，载自其它网页。-amba AHB bus parts from the machine connected to the interface with the wording set out from other pages.
Platform: | Size: 2048 | Author: yang sally | Hits:

[VHDL-FPGA-Verilog] AHB_to_Wishbone_Verilog

Description: 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
Platform: | Size: 2077696 | Author: jinjin | Hits:

[ARM-PowerPC-ColdFire-MIPS] AMBA-AHB-APB-BUS

Description: 常见ARM架构的AMBA、AHB、APB总线的介绍，对ARM的总线有个清晰的了解，对各模块的关系也可深入了解-Common ARM architecture AMBA, AHB, APB bus introduction of ARM' s have a clear understanding of the bus, on the relationship between the modules can also be in-depth understanding of
Platform: | Size: 50176 | Author: sp | Hits:

[VHDL-FPGA-Verilog] AHB

Description: AMBA片内总线结构的设计，给需要的人啊。-AMBA on-chip bus architecture is designed to need ah.
Platform: | Size: 466944 | Author: 陈锴 | Hits:

[VHDL-FPGA-Verilog] AHB

Description: 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
Platform: | Size: 438272 | Author: 陈锴 | Hits:

[VHDL-FPGA-Verilog] AHB-BUS-AND-SLAVE-CODE-USING-VERILOG

Description: AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
Platform: | Size: 34816 | Author: xuqinjiang | Hits:

[VHDL-FPGA-Verilog] AHB_slave-ram

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
Platform: | Size: 1024 | Author: 吴亮 | Hits:

[VHDL-FPGA-Verilog] AHB-Default-Slave-Module

Description: AMBA2.0版本AHB总线缺省从设备设计方面的技术支持，参考ARM公司AMBA技术手册。对AHB缺省从设备电路的接口、基本逻辑等方面进行介绍。-AMBA2.0 version of the default from the AHB bus support equipment design, ARM AMBA technology reference manual. Default on the AHB slave interface circuit, the basic logic, etc. are introduced.
Platform: | Size: 73728 | Author: 杨宗凯 | Hits:

[VHDL-FPGA-Verilog] AHB-Decoder-Module

Description: AMBA2.0版本AHB总线译码单元设计方面的技术支持，参考ARM公司AMBA技术手册。对AHB译码单元电路的接口、基本逻辑等方面进行介绍。-AMBA2.0 version of the AHB bus decoding unit design technical support, refer to ARM AMBA technical manual. AHB decoder unit circuit of the interface, basic logic, etc. are introduced.
Platform: | Size: 90112 | Author: 杨宗凯 | Hits:

[VHDL-FPGA-Verilog] ahb

Description: verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
Platform: | Size: 36864 | Author: 落叶无情1992 | Hits:

[Other] AHB RAM

Description: Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Platform: | Size: 21811200 | Author: 容止 | Hits:
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