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[VHDL-FPGA-Verilog] te187

Description: 基于高速串行BCD 码除法的数字频率计的设计-Based on high-speed serial BCD code of the digital frequency divider Design
Platform: | Size: 208896 | Author: 张贺寅 | Hits:

[Other] DIVIDER

Description: 多倍（次）分频器。 多倍（次）分频器-BCD Code Conversion
Platform: | Size: 1024 | Author: 橡树 | Hits:

[VHDL-FPGA-Verilog] VerilogSourceCode

Description: 乘法器、除法器、多路选择器、编码器、BCD码转换、加法器、减法器、状态机、四位比较器、数码管、串口、跑马灯、电子钟-Multiplier, divider, multiplexer, encoder, BCD code converter, adder, subtractor, state machines, four more players, digital control, serial port, marquees, electronic clock
Platform: | Size: 2050048 | Author: zhaozhifang | Hits:

[VHDL-FPGA-Verilog] final

Description: 频率计设计的各个模块连接的总程序，即把分频器、控制器、计数器、闸门控制、锁存器、显示器都连接起来，测试频率范围为：10Hz～100MHz 第一档：闸门时间为1S时，最大读数为999.999KHz 第二档：闸门时间为0.1S时，最大读数为9999.99KHz 第三档：闸门时间为0.01S时，最大读数为99999.9KHz。 用六位BCD七段数码管显示读数。-The various modules connected to the total program, frequency meter design that are connected to the divider, controllers, counters, gate control, latches, display, test frequency range of: 10Hz ~~ 100MHz speed: gate time 1S when maximum readings 999.999KHz second gear: the gate time 0.1S maximum reading 9999.99KHz third tranche: gate time 0.01S, the maximum readings for 99999.9KHz. Readings with six BCD seven segment LED display.
Platform: | Size: 1024 | Author: 李雪 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL初级编程实例：动态扫描显示程序、分频器设计程序、8位移位寄存器、BCD计数器设计(任意进制)等等。-VHDL the primary programming examples: dynamic scanning display program, the divider design process, the 8-bit shift register, BCD counter design (any hex), and so on.
Platform: | Size: 11264 | Author: 罗梵 | Hits:

[VHDL-FPGA-Verilog] second

Description: 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design, and simulation waveform, and there is a corresponding report. The report also includes a BCD/7 segment decoder IC 74LS47 simulation, single-tube type stable operating point voltage divider bias circuit simulation and 8 quiz Responder circuit design
Platform: | Size: 465920 | Author: 文闯 | Hits:

[VHDL-FPGA-Verilog] 7-BCD

Description: 7段数码管控制接口程序和对初始频率为50MHZ的时钟的分频程序-7-segment control interface program and the initial frequency of 50MHZ clock divider program
Platform: | Size: 1024 | Author: 李康康 | Hits:

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