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[Embeded-SCM Develop] bist

Description: 芯片测试讲义，讲的BIST内容。即芯片的自测。
Platform: | Size: 95821 | Author: CoCo | Hits:

[VHDL-FPGA-Verilog] BIST_Circuits

Description: BIST 电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-BIST circuits IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 5120 | Author: 周华茂 | Hits:

[Embeded-SCM Develop] bist

Description: 芯片测试讲义，讲的BIST内容。即芯片的自测。-Chip test notes, the contents of said BIST. That is, self-rated chips.
Platform: | Size: 95232 | Author: CoCo | Hits:

[Books] ElectronicTesting

Description: 数字存储器和混合信号超大规模集成电路本书系统地介绍了数字、存储器和混合信号VLSI系统的测试和可测试性设计。该书是根据作者多年的科研成果和教学实践，结合国际上关注的最新研究热点并参考大量的文献撰写的。全书共分三个部分。第一部分是测试基础，介绍了测试基本概念、测试设备、测试经济学和故障模型。第二部分是测试方法，详细论述了组合和时序电路的测试生成、存储器测试、基于DSP和基于模块的模拟与混合信号测试、延迟测试和IDDQ测试等。第三部分是可测试性设计，包括扫描设计、BIST、边界扫描测试、模拟测试总线标准和基于IP芯核的SOC（System on a chip）测试。
Platform: | Size: 33169408 | Author: soctest | Hits:

[Books] DFT_BIST_for_SOC

Description: 用于SoC设计的DFT和BIST，讲解了在SOC设计中需要考虑的可测性设计问题 -SoC design for DFT and BIST, explain in the SOC design need to consider design-for-test issues
Platform: | Size: 95232 | Author: godname | Hits:

[Industry research] dokserv

Description: A BIST (BUILT-IN SELF-TEST) STRATEGY FOR MIXED-SIGNAL INTEGRATED CIRCUITS
Platform: | Size: 1278976 | Author: dyx | Hits:

[Editor] getPDF

Description: 本文分析的环境，利用内建自测试（ BIST ）和自动测试设备（ ATE ）和提出了封闭形式表达的故障覆盖率的函数数量的BIST的和ATE测试向量。-Analysis and Measurement of Fault Coverage in a Combined ATE and BIST Environment
Platform: | Size: 518144 | Author: 被遗忘 | Hits:

[Windows Develop] fwrememorybistvcestudent

Description: bist method for simulation of micro controller
Platform: | Size: 317440 | Author: david | Hits:

[VHDL-FPGA-Verilog] bist

Description: design for test Test and Design-for-Test for memory bist-design for test
Platform: | Size: 1435648 | Author: sky | Hits:

[Other] BISTProject

Description: BIST test doing project, in verilog.
Platform: | Size: 826368 | Author: kk | Hits:

[VHDL-FPGA-Verilog] uart

Description: UART design with bist capability
Platform: | Size: 24576 | Author: veerender | Hits:

[VHDL-FPGA-Verilog] BIST

Description: A simple BIST in VHDL. It contains a LFSR with an SISR.
Platform: | Size: 405504 | Author: bommeren | Hits:

[VHDL-FPGA-Verilog] LIP2908CORE_membist

Description: Mem bist Verilog Module
Platform: | Size: 107520 | Author: jc | Hits:

[VHDL-FPGA-Verilog] FPGST

Description: FPGA的时延故障测试方法 BIST的动态可重构-FPGA delay fault test method of dynamically reconfigurable BIST
Platform: | Size: 318464 | Author: tive | Hits:

[Mathimatics-Numerical algorithms] rage

Description: 逻辑内建自测试高故障覆盖率设计Logic BIST design of high fault coverage-Logic BIST design of high fault coverage
Platform: | Size: 271360 | Author: vid2008 | Hits:

[VHDL-FPGA-Verilog] rategy

Description: FPGA的板级BIST设计和实现策略FPGA board-level BIST design and implementation strategy-FPGA board-level BIST design and implementation strategy
Platform: | Size: 243712 | Author: gu | Hits:

[VHDL-FPGA-Verilog] doc

Description: BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this project, the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. In this project, it has been demonstrated that accumulator based compaction scheme
Platform: | Size: 243712 | Author: sreekanth p | Hits:

[VHDL-FPGA-Verilog] BIST-CODE

Description: BIST IS A BUILT IN SELF TEST FOR VHDL
Platform: | Size: 923648 | Author: sandeep | Hits:

[VHDL-FPGA-Verilog] bist 2017 paper

Description: A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains.
Platform: | Size: 1568768 | Author: Maddy619 | Hits:

[VHDL-FPGA-Verilog] bist pattern generator

Description: document of bist with low power generator
Platform: | Size: 1816576 | Author: vankay | Hits:

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[Embeded-SCM Develop] bist

[VHDL-FPGA-Verilog] BIST_Circuits

[Embeded-SCM Develop] bist

[Books] ElectronicTesting

[Books] DFT_BIST_for_SOC

[Industry research] dokserv

[Editor] getPDF

[Windows Develop] fwrememorybistvcestudent

[VHDL-FPGA-Verilog] bist

[Other] BISTProject

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] BIST

[VHDL-FPGA-Verilog] LIP2908CORE_membist

[VHDL-FPGA-Verilog] FPGST

[Mathimatics-Numerical algorithms] rage

[VHDL-FPGA-Verilog] rategy

[VHDL-FPGA-Verilog] doc

[VHDL-FPGA-Verilog] BIST-CODE

[VHDL-FPGA-Verilog] bist 2017 paper

[VHDL-FPGA-Verilog] bist pattern generator

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