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[Other resource] CAN协议控制器的Verilog实现

Description: 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
Platform: | Size: 39048 | Author: wl | Hits:

[Other Embeded program] CAN协议控制器的Verilog实现

Description: 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
Platform: | Size: 38912 | Author: wl | Hits:

[Compress-Decompress algrithms] canbus(FPGA)

Description: 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run.
Platform: | Size: 862208 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] SPI_Code(Verilog)

Description: SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用-SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses
Platform: | Size: 5120 | Author: 高兵 | Hits:

[VHDL-FPGA-Verilog] can_IPCORE

Description: CAN总线IPCORE，采用Verilog HDL语言实现。-CAN bus IPCORE, using Verilog HDL language.
Platform: | Size: 61440 | Author: feifei | Hits:

[Software Engineering] Code

Description: DSP学习板上的例子程序包括 AD转换 CAN总线 SPI SCI -Examples of on-board DSP learning process includes the AD conversion CAN Bus SPI SCI
Platform: | Size: 1227776 | Author: qwe | Hits:

[VHDL-FPGA-Verilog] can

Description: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Platform: | Size: 89088 | Author: 戴求淼 | Hits:

[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] canbus

Description: verilog 和VHDL实现的can总线接口代码-the realization of verilog and VHDL code of the can bus interface
Platform: | Size: 95232 | Author: bsyy | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 通过I2C接口读写EEPROM 在本项目中，我们利用Verilog HDL实现了部分I2C总线功能，并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果，我们将读写的数据同时显示在七段数码管上，并设定读写的数据从0到255不断循环，这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some of the I2C bus function, and can be carried out through the bus, read and write operations on the AT24C02. To read and write eeprom in order to facilitate observation of the results, we will read and write data simultaneously displayed in the seven-segment digital tube, and set read and write data from 0 to 255 in cycles, so that can be easily compared.
Platform: | Size: 8192 | Author: andy | Hits:

[VHDL-FPGA-Verilog] canbus

Description: 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 1079296 | Author: 陈阳 | Hits:

[Software Engineering] can-verilog

Description: 汽车工业系统里面的电气设备常用的总线控制-Automotive systems commonly used in electrical equipment inside the bus control
Platform: | Size: 537600 | Author: sangpeng | Hits:

[VHDL-FPGA-Verilog] can_latest.tar

Description: VHDL/VERILOG FOR CAN BUS Core
Platform: | Size: 1176576 | Author: mss | Hits:

[VHDL-FPGA-Verilog] can

Description: can总线的verilog设计与实现，很好的资料哦-the implention of can bus with verilog
Platform: | Size: 122880 | Author: pengyong | Hits:

[VHDL-FPGA-Verilog] design-of-CAN-based-on-VHDL

Description: 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness
Platform: | Size: 2615296 | Author: chen xinwei | Hits:

[VHDL-FPGA-Verilog] can-bus

Description: CAN总线控制器的VERILOG工程文件,很实用，工程是ISE可以打开，也可以只使用工程里面的代码-can bus project with VERILOG
Platform: | Size: 1097728 | Author: mike | Hits:

[VHDL-FPGA-Verilog] verilog

Description: opencore can bus verilog design file-opencore can bus verilog design file
Platform: | Size: 93184 | Author: zhixiaowen | Hits:

[VHDL-FPGA-Verilog] CAN-BUS-with-Verilog

Description: CAN 总线的verilog是实现与设计 很好的资料-implementation of can bus use verilog
Platform: | Size: 78848 | Author: 李研 | Hits:

[Other] 20 CAN总线实验

Description: 基于can总线的，Verilog源代码分享，可以在Z7030芯片开发板进行演示。(Based on the CAN bus, Verilog source code sharing, can be demonstrated in the Z7030 chip development board.)
Platform: | Size: 1292288 | Author: haotian1989 | Hits:

[VHDL-FPGA-Verilog] CAN总线，I2C，USB等的FPGA实现源码

Description: 控制器局域网总线协议的Verilog代码(The Verilog code of the CAN bus protocol)
Platform: | Size: 1910784 | Author: walawalapi | Hits:
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