Description: 这是一个I2C串行数据通信协议以VHDL硬件描述语言实现的IP核,可直接编译运行-I2C serial data communication protocol to VHDL hardware description language of the IP core can be directly translated Operation Platform: |
Size: 6144 |
Author:陈州徽 |
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Description: PCI局部总线的中文教程,可以加快你对PCI总线通讯协议的学习理解。-PCI Local Bus Guide in Chinese, you can speed up your PCI bus communication protocol of the study and understanding. Platform: |
Size: 1171456 |
Author:何风 |
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Description: 串口通讯协议,你您可以自己建个工程,再将需要的VHDL文本,添加到工程中,理解程序在仿真!-Serial communication protocol, you can build your project, and then need VHDL text, added to the project, understand the procedures in the simulation! Platform: |
Size: 10240 |
Author:张亚伟 |
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Description: zigbee协议中,可以用来进行无线定位的处理器模块说明-zigbee protocol, can be used for wireless location description of the processor module Platform: |
Size: 155648 |
Author:dd |
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Description: UIP完整的协议栈,可以应用于8位或16位单片机作web-server功能,该协议栈的一个显著的优点就是需要的空间极小。-UIP complete protocol stack, can be applied to 8-bit or 16-bit single-chip microcomputer for the web-server functionality, the protocol stack, a significant advantage is that a very small space requirements. Platform: |
Size: 2199552 |
Author:张勃 |
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Description: 本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上-This code is to achieve a lwIP protocol stack can be ported to other types of embedded operating systems such as the type Platform: |
Size: 355328 |
Author:张日 |
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Description: 适用于满足I2C协议的flash读/写操作程序,只需要设置要读/写的字节数,就可以直接使用!-Applicable to meet the I2C protocol flash read/write operations, only need to set to read/write number of bytes can be used directly! Platform: |
Size: 3072 |
Author:xiaoyuer |
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Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数,由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse. Platform: |
Size: 37888 |
Author: |
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Description: Verilog HDL的程式,上網找到SPI程式,
vspi.v這程式相當好用可用來接收與傳送SPI,並且寫了一個傳輸信號測試,spidatasent.v這程式就是傳送的資料,分別為00 66... 01 77...... 02 55這樣的資料,並透過MAX+PULS II軟體進行模擬,而最外層的程式是test_createspi.v!-Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v! Platform: |
Size: 145408 |
Author:Rick |
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Description: 这是CAN总线控制器的IP核,源码是由Verilog HDL编写的。其硬件结构与SJA1000类似,满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B. Platform: |
Size: 61440 |
Author:普林斯 |
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Description: CAN通信协议的硬件描述语言代码,用于FPGA的总线接口控制器开发-CAN communication protocol of the hardware description language code for the FPGA bus interface controller development Platform: |
Size: 862208 |
Author:shigengxin |
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Description: 可用来破解分析西门子200 PLC与模块的通讯协议,基于ALTERA CPLD EPM240的设计.
需要配合分析板配套使用。-Analysis can be used to crack the Siemens 200 PLC and the communication protocol modules, based on the ALTERA CPLD EPM240 design. The need to tie in with the analysis supporting the use of panels. Platform: |
Size: 2048 |
Author:wuzhen |
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Description: UTMI全称为 USB2.0 Transceiver Macrocell Interface,此协议是针对USB2.0的信号特点进行定义的,分为8位或16位数据接口。目的是为了减少开发商的工作量,缩短产品的设计周期,降低风险。此接口模块主要是处理物理底层的USB协议及信号,可与SIE整合设计成一专用ASIC芯片,也可独立作为PHY的收发器芯片,下以8位接口为例介绍PHY的工作原理及设计特点。
-UTMI called USB2.0 Transceiver Macrocell Interface, this agreement is a signal for USB2.0-defined characteristics, is divided into 8-bit or 16-bit data interface. The purpose is to reduce the workload of developers to shorten product design cycles, reduce risk. This interface module is mainly to deal with the underlying physics of the USB protocol and signaling, can be integrated with the SIE designed a dedicated ASIC chips, can also be independent of the transceiver as a PHY chip, the next eight to PHY interface as an example to introduce the working principle and design features. Platform: |
Size: 210944 |
Author:leixueyan |
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Description: 用VHDL编写的EPP通信协议,可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes Platform: |
Size: 1024 |
Author:Roy |
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Description: Design approach for VHDL and FPGA Implementation of
Automotive Black Box using CAN Protocol Platform: |
Size: 128000 |
Author:brethurtkid |
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Description: usb 2.0协议的ip核,可用,里面程序有文档说明-usb 2.0 protocol ip core, can be used, which procedures are documented Platform: |
Size: 208896 |
Author:KKK |
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Description: 本系统设计利用FPGA设计了一个接在电脑串口上的一个DMX512协议的转接卡,它可以让你的电脑变成一台超强的电脑灯控制台或者调光台、LED控制器等。通过电脑软件,可以控制电脑灯或者其他DMX512协议的设备,比如LED灯、激光灯、PAR灯、DJ设备等等。
本系统还有体积小巧携带方便等特点,足够一般的娱乐场所、多功能厅、会议厅等场所使用,同时采用电脑进行灯光的控制,也可以提升工程的技术含量,显得更高科技。通过简单更改DMX模块的UART部分,还可以将串口转换usb接口,不过由于手头上的FPGA开发板没有USB接口,所以使用UART接口进行测试。
-The system design using FPGA, a serial port on the computer then a DMX512 protocol adapter, it can make your computer into a super computer console or lighting console lights, LED controller. Through computer software, can control lights or other DMX512 protocol computer equipment, such as LED lights, laser lights, PAR lamps, DJ equipment. The system also features compact, portable and so on, is sufficient for most of the entertainment, function rooms, conference rooms and other places to use, while using computer control of lighting can also enhance the project s technical content, appears to higher technology. DMX module by simply changing the UART portion can also convert usb serial interface, however, because the FPGA development board on hand no USB interface, so tests using the UART interface.
Platform: |
Size: 2223104 |
Author:swekey |
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Description: 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计,实现其功能,并且能够在FPGA开发平台Quartos上通过仿真验证,证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness Platform: |
Size: 2615296 |
Author:chen xinwei |
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