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[VHDL-FPGA-Verilog] 并口的CPLD烧录线，通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)

Description: 并口的CPLD烧录线，通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
Platform: | Size: 2302730 | Author: mikeldm@163.com | Hits:

[VHDL-FPGA-Verilog] CPLD 與 61LV256 SRAM 驱动 TFT

Description: CPLD 與 61LV256 SRAM 驱动 4.3 吋的 TFT,附 Verilog 語言範例.
Platform: | Size: 2896 | Author: xyz543 | Hits:

[Embeded-SCM Develop] verilog实例 [43项]

Description: 嵌入式可编程器件CPLD的典型实例 压缩包，共计43个源码文件。 使用ALTERA的 Muxplus 软件即可编辑仿真 相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
Platform: | Size: 181248 | Author: 吴旭辉 | Hits:

[Embeded-SCM Develop] JTAG仿真器CPLD

Description: JTAG仿真器CPLD -JTAG Emulator CPLD
Platform: | Size: 345088 | Author: 李秉 | Hits:

[VHDL-FPGA-Verilog] 结合XILINXCPLD RS232通信(verilog)

Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Platform: | Size: 121856 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] 用cpld实现曼彻斯特编码

Description: 用cpld实现曼彻斯特编码 用verilog HDL进行曼彻斯特编码，用于通信中-cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication
Platform: | Size: 4096 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] wavegenerator_testbench

Description: 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
Platform: | Size: 4096 | Author: liu | Hits:

[Special Effects] videofram

Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Platform: | Size: 1024 | Author: 陈刚峰 | Hits:

[Post-TeleCom sofeware systems] CPLD_example_50

Description: 50个各种不同功能的CPLD程序例子，拿来就可以用，每个都经过了综合测试，非常实用-50 different functional CPLD procedures example, can be taken out, after each of the comprehensive test very useful
Platform: | Size: 490496 | Author: 曾某人 | Hits:

[Embeded-SCM Develop] VerilogHDL88

Description: veriloghdl语言工具书，适合初次了解cpld和fpga工程师学习使用-veriloghdl language tool, suitable for initial understanding of fpga and cpld engineers learning
Platform: | Size: 9424896 | Author: 刘江山 | Hits:

[Software Engineering] keyscan

Description: 4×4键盘扫描的verilog 代码,在CPLD板上实现-4 × 4 keyboard scan Verilog code, the CPLD on the board realize
Platform: | Size: 1024 | Author: fang zhou | Hits:

[VHDL-FPGA-Verilog] ccd-in-verilog

Description: ALTERA关于CCD的一些verilog程序，都通过运行无误的。-ALTERA on a number of Verilog CCD procedures, both by running unmistakable.
Platform: | Size: 14336 | Author: 邹振兴 | Hits:

[VHDL-FPGA-Verilog] code

Description: CPLD驱动VGA显示器的VERILOG源代码．-VGA display driver CPLD Verilog source code.
Platform: | Size: 236544 | Author: xuhong | Hits:

[VHDL-FPGA-Verilog] vhdlkey7279

Description: cpld，环境是quartusii中vhdl语言开发7279读写键盘程序-cpld, the environment is quartusii in VHDL language to develop reading and writing 7279 keyboard program
Platform: | Size: 610304 | Author: 夏杰 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 好东东，大家都来看看一啊克混合后 学cpld的一定需要-Dongdong good, we all take a look at ah 1 grams of a mixture of a certain need to learn CPLD
Platform: | Size: 235520 | Author: | Hits:

[VHDL-FPGA-Verilog] 8051-Verilog

Description: 使用CPLD仿真8051核,内有源程序和说明,来之不易-CPLD simulation using 8051 nuclear, which has source code and description, the hard-won
Platform: | Size: 90112 | Author: 梁志洪 | Hits:

[VHDL-FPGA-Verilog] 7led

Description: dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
Platform: | Size: 91136 | Author: pp | Hits:

[VHDL-FPGA-Verilog] clock

Description: dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
Platform: | Size: 79872 | Author: pp | Hits:

[VHDL-FPGA-Verilog] rs232

Description: dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
Platform: | Size: 121856 | Author: pp | Hits:

[Embeded-SCM Develop] 从零开始学CPLD和VERILOG HDL

Description: 从零开始学CPLD和VERILOG HDL(Learn CPLD and VERILOG HDL from zero)
Platform: | Size: 32979968 | Author: Jerry20170718 | Hits:
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