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[Other] SojournerProgram

Description: 这里是我在学校时所写的一些程序，其中有些Java程序可能要重新编译一下才能运行，具体如下：C Course Disign——C语言编写的时钟程序Very Simple CPU——CPU仿真工具StudentQuery——基于SQL语言数据库的学籍管理系统Theory of Computation——一些关于计算理论算法的实现，详见内附说明Hotel——酒店管理系统另外还有一些硬件VHDL方面的程序，整理好后会陆续上传-here at school I wrote some of the procedures, some of which may be Java recompile about to run, as follows : C Course Disign -- C language clock procedures Very Simple CPU -- CPU simulation tool StudentQuery -- based on SQL database the Information Management Theory of Computation -- some theoretical algorithm for the calculation of the realization of enclosing detailed statement Hotel -- hotel management system there are some VHDL hardware of the procedures, will be sorted out gradually upload
Platform: | Size: 612380 | Author: Sojourner | Hits:

[Other] SojournerProgram

Description: 这里是我在学校时所写的一些程序，其中有些Java程序可能要重新编译一下才能运行，具体如下：C Course Disign——C语言编写的时钟程序Very Simple CPU——CPU仿真工具StudentQuery——基于SQL语言数据库的学籍管理系统Theory of Computation——一些关于计算理论算法的实现，详见内附说明Hotel——酒店管理系统另外还有一些硬件VHDL方面的程序，整理好后会陆续上传-here at school I wrote some of the procedures, some of which may be Java recompile about to run, as follows : C Course Disign-- C language clock procedures Very Simple CPU-- CPU simulation tool StudentQuery-- based on SQL database the Information Management Theory of Computation-- some theoretical algorithm for the calculation of the realization of enclosing detailed statement Hotel-- hotel management system there are some VHDL hardware of the procedures, will be sorted out gradually upload
Platform: | Size: 3420160 | Author: Sojourner | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPU模拟

Description: 本软件实现了模拟cpu的基本工作原理和工作过程，可以实现机器指令级和微指令级的操作，同时又可在编辑窗口内自行变编辑指令，对于初学者学习CPU的结构和工作原理是很有帮助的-the software simulation cpu the basic working principle and the process, the machine can achieve the task of instruction-level and the operational level, but also within the edit window to change editorial direction, the CPU for beginners to learn the structure and working principle is very helpful
Platform: | Size: 120832 | Author: 叶靥 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips_creative

Description: 一个完整的MIPS CPU，创新设计，浙江大学某学生作品，有完整的说明文档、仿真文件和测试文件，可以直接综合和仿真。-a complete MIPS CPU, innovative design, a student of Zhejiang University works with complete documentation, simulation and test documents, and can be directly integrated simulation.
Platform: | Size: 1866752 | Author: 梁文锋 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[source in ebook] CPU_use

Description: 使用VHDL语言编写的简单8位流水线CPU 它有六级流水功能，通过仿真 可以下载到实验箱，也有波形仿真-use VHDL to prepare a simple eight pipelined CPU it has six functional water, Simulation experiments can be downloaded to the box, a waveform simulation
Platform: | Size: 1530880 | Author: 邮件 | Hits:

[VHDL-FPGA-Verilog] CPUNEW

Description: MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构-ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative
Platform: | Size: 50176 | Author: yyy | Hits:

[VHDL-FPGA-Verilog] controlunit

Description: CPU设计中的controlunit源码，其中附带了时序仿真。通过Sequencing Logic 产生 control_signals,具体的信号可在controlsignal.mif文件中直接修改。 -CPU design controlunit source, which comes with timing simulation. Sequencing Logic generated through control_signals, specific signals can directly modify the controlsignal.mif document.
Platform: | Size: 328704 | Author: ck | Hits:

[VHDL-FPGA-Verilog] ModelSimSimulateCPU

Description: 应用VHDL编写程序， 利用ModelSim仿真CPU-Application of VHDL programming, using ModelSim simulation CPU
Platform: | Size: 57344 | Author: hjy | Hits:

[Other] computer

Description: 在LP2900工作平台上，利用MAX+plusII开发软件，设计各个模块编程实现基本模型计算机，其中最主要的是CPU的设计。 独立完成运算器的设计，并下载仿真 -Working platform in the LP2900, using MAX+ PlusII to develop software, design each module to achieve the basic model of programming computers, among which is the CPU design. An independent operator to complete the design, and download the simulation
Platform: | Size: 71680 | Author: 杨继伟 | Hits:

[Software Engineering] cpudesignvhd

Description: 内包含在VHDL环境下的CPU设计原理图和代码以及最后的仿真过程-Within the VHDL environment is included in the CPU design schematics and code, as well as the final simulation
Platform: | Size: 77824 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended and provided for simulation.
Platform: | Size: 4490240 | Author: 灿烂六月 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 利用vhdl模拟实现CPU的功能，实现其中的加减乘除等多种运算-CPU utilization of vhdl simulation of the realization of the function, the realization of which, such as addition and subtraction, multiplication and division multiple computing
Platform: | Size: 1013760 | Author: 张宁 | Hits:

[VHDL-FPGA-Verilog] Microprogramcontroller

Description: 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
Platform: | Size: 752640 | Author: 糖糖 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 包含CPU每部分器件的编写，通过改写RAM内容，可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
Platform: | Size: 2151424 | Author: Sophie | Hits:

[VHDL-FPGA-Verilog] POC_all

Description: poc即为cpu与外部设备，比如打印机的接口，用VHDL的编程来实现poc功能的仿真-poc is the cpu with an external device, such as the printer' s interface, programming with VHDL simulation capabilities to achieve poc
Platform: | Size: 920576 | Author: 苏佳佳 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:

[ARM-PowerPC-ColdFire-MIPS] cpu

Description: 16位的5级流水线cpu 采用vhdl代码 modelsim编译仿真-5-stage pipeline 16-bit cpu compiled simulation using modelsim vhdl code
Platform: | Size: 5120 | Author: sean | Hits:

[Software Engineering] CPU

Description: 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构，实现了cpu的基本功能如：加减乘除运算，跳转等。此外，里面有一个17位的ROM区，是存储指令的。你可以写出一段17位的指令代码，并放入ROM区，该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan University. This is an 8-bit CPU design VHDL implementation. The CPU based on RISC architecture to achieve the basic functions, such as cpu: arithmetic operations, jumps and so on. In addition, there are a ROM area 17, is stored in the instruction. You can write some 17 of the instruction code, and placed in the ROM area, the CPU will automatically run the result. Compression bag is the source code and design requirements of our time. When the final commissioning source code is placed in the address 0 17 of Fibonacci numbers (Fibonacci Numbers) instruction. You can see the results of the simulation by modelsim.
Platform: | Size: 520192 | Author: ljt | Hits:

[VHDL-FPGA-Verilog] CPU

Description: a very useful vhdl source code for simulation and test the parwan cpu navabi vhdl book-a very very useful vhdl source code for simulation and test the parwan cpu navabi vhdl book
Platform: | Size: 189440 | Author: a | Hits:
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