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[VHDL-FPGA-Verilog] fdpll

Description: 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: | Size: 2048 | Author: 陈德炜 | Hits:

[Software Engineering] 010919.pdf

Description: 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL description and achieve functional simulation, followed by graphic shows
Platform: | Size: 286720 | Author: 巢海步 | Hits:

[VHDL-FPGA-Verilog] VHDLDPLL

Description: 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
Platform: | Size: 167936 | Author: 李湘鲁 | Hits:

[VHDL-FPGA-Verilog] dpll0226

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 184320 | Author: sss | Hits:

[Books] changyongmokuai

Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
Platform: | Size: 793600 | Author: 1 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: ＦＰＧＡ实现全数字锁相环，利用硬件描述评议verilog HDL，顶层文件ＤＰＬＬ．Ｖ-FPGA realization of all-digital phase-locked loop, using hardware description Convocation verilog HDL, the top-level document DPLL. V
Platform: | Size: 4096 | Author: YP | Hits:

[VHDL-FPGA-Verilog] FPGA-DPLL

Description: 基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
Platform: | Size: 181248 | Author: lixu | Hits:

[Other] DPLL

Description: 一种可编程的全数字锁相环的丝线,可以用来做一个小的课程设计-A programmable DPLL thread can be used to do a small course design
Platform: | Size: 140288 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] shuzisuoxiang

Description: 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of applications. With the traditional analog circuit implementation of the PLL in comparison, DPLL with high accuracy, free from the impact of temperature and voltage, loop bandwidth and center frequency adjustable programming, easy to build a high-order phase-locked loop, etc..
Platform: | Size: 1024 | Author: hellen | Hits:

[VHDL-FPGA-Verilog] dpll

Description: dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
Platform: | Size: 1024 | Author: hsj | Hits:

[Other] dpll

Description: 锁相环的基本原理，设计结构，及实现过程介绍-The basic principles of phase-locked loop, design structure, and the realization of the process of introducing
Platform: | Size: 1664000 | Author: 张兆伟 | Hits:

[Other] DPLL

Description: pll 的数字实现大家 支持 第一次 传-pll digital impliment
Platform: | Size: 49152 | Author: zhangfuquan | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[Software Engineering] DPLL

Description: 基于VHDL语言的DPLL电路的设计，给出了设计方案和部分源代码 -DPLL
Platform: | Size: 193536 | Author: zhao peng | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 数字锁相环频率合成器的vhdl实现的源代码-Digital PLL Frequency Synthesizer vhdl source code to achieve
Platform: | Size: 539648 | Author: sunnyhp | Hits:

[VHDL-FPGA-Verilog] NCO_sin

Description: 介绍了压控震荡器(VCO)的设计，压缩包里面有VHDL语言编写的代码，在仿真器上可以实现仿真结果，非常不错 -The VHDL code of VCO
Platform: | Size: 3072 | Author: 吴晓英 | Hits:

[VHDL-FPGA-Verilog] FPGA-based-design-of-DPLL

Description: 采用VHDL设计的全数字锁相环电路设计，步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
Platform: | Size: 416768 | Author: 阿啊 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:

[VHDL-FPGA-Verilog] VHDL-FPGA-DLL

Description: 自动检测中英文中译英英译中百度翻译 翻译结果（中 > 英）复制结果 A VHDL language based on all digital phase-locked loop DPLL VHDL realization-自动检测中英文中译英英译中百度翻译 翻译结果（中 > 英）复制结果 A VHDL language based on all digital phase-locked loop DPLL VHDL realization
Platform: | Size: 230400 | Author: ldd | Hits:
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