Description: 几个BOC 信号的分析例程，全球卫星导航系统将普遍采用BOC调制信号作为扩频测距信号，BOC信号自相关函数呈现多个相关峰，传统扩频接收机所用的延迟锁定环（DLL）无法对该信号正确地进行码相位的-Several BOC signal analysis routines, the global satellite navigation system will be widely used BOC modulation signal as a spread spectrum ranging signal, BOC signal auto-correlation function shows a number of correlation peak, the traditional spread-spectrum receiver using delay locked loop (DLL) the signal can not be correctly code phase Platform: |
Size: 7168 |
Author:andy |
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Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O Platform: |
Size: 132096 |
Author:xbl |
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Description: gps延迟锁定环中对热噪声的模拟，考虑了热噪声对跟踪精度的影响，很不错的-gps delay locked loop in the thermal noise of the simulation, taking into account thermal noise on the impact of tracking accuracy, very good Platform: |
Size: 1024 |
Author:li jian |
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Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型
化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了
三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic, Platform: |
Size: 546816 |
Author:John |
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Description: DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3,
Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal
at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN).
The locked output (LOCKED) is high when the two signals are in phase. The signals
are considered to be in phase when their rising edges are within a specified time (ps)
of each other. Platform: |
Size: 106496 |
Author:shad |
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Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。
PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。
-Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time. Platform: |
Size: 553984 |
Author:裴雷 |
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Description: 详细讲述了直接序列扩频差分锁相环的文章，包含具体的算法结构，并附有仿真结果。-A novel differentially coherent delay-locked loop(DCDLL) for accurate code tracking is proposed for direct sequence spread spectrum systems. Due to the use of the differential
decoder and exactly one correlator, the proposed scheme avoids
the problems of gain imbalance. The tracking error variance is
derived by linear analysis. When the proposed DCDLL scheme is
applied in ranging with additive white Gaussian noise (AWGN)
channel, the performance of the proposed DCDLL scheme is
about 1.4 dB better than that of one-correlator tau–dither loop
(TDL), and near that of noncoherent DLL. Platform: |
Size: 76800 |
Author:caiyh |
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Description: 在matlab与SystemGenerator的平台下实现零阶时延数字正切锁相环。此模块最终能达到与输入信号同频率。-In the matlab, and SystemGenerator the platform, zero-order delay tangent digital phase-locked loop. This module is ultimately to reach input signal with the same frequency. Platform: |
Size: 27648 |
Author: |
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Description: 本书介绍了部分关键算法的VLSI有效实现结构。全书共8章,包括伪噪声序列基本理论、数字锁相环的基本原理、数字下变频器的算法设计、直接数字频率合成器的基本理论和基于有限域的数字压控振荡器、数字抑制载波跟踪环的算法设计、伪噪声序列的快速捕获算法、数字延迟跟踪环的算法设计,以及它们的VLSI结构等内容.-This book presents some of the key algorithm for VLSI effective realization of the structure. The book is Chapter 8, including the basic principles of the basic theory of pseudo-noise sequence, the digital phase-locked loop, the algorithm design of the digital down converter, the basic theory of direct digital frequency synthesizer based on the finite field of digital voltage-controlled oscillator, digital suppressed carrier tracking loop of the algorithm design, rapid acquisition of pseudo-noise sequence algorithm, digital delay in the tracking loop of the algorithm design, and VLSI architecture. Platform: |
Size: 5265408 |
Author: |
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Description: 几个BOC 信号的分析例程，全球卫星导航系统将普遍使用BOC调制信号作为扩频测距信号，BOC信号号自相关函数呈现多个相关峰，传统扩频接收机所用的延迟锁定环（DLL）无法对该信号正确地进行码相位的
-Several BOC signal analysis routines, the global satellite navigation system will generally use the BOC modulation signal as a spread spectrum ranging signal, BOC signal autocorrelation function presents multiple correlation peaks, the traditional spread spectrum receiver with the delay locked loop (DLL ) can not be the signal code phase Platform: |
Size: 8192 |
Author:yanyantiao |
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Description: a new circuit topology of a
phase-locked loop that can be used for synchronising a singlephase
wind turbine generator (WTG) with the low voltage utility
grid. The circuit is based on the time-delay digital tanlock loop
(TDTL) architecture and was modelled and simulated using
Simulink/MATLAB. The results presented demonstrate the
ability of the circuit not only to synchronise a WTG with the grid,
but also to re-gain synchronization following a sudden
disturbance in the grid voltage. The simulated disturbances
included a ramp and a multi-step change in the phase of the grid
voltage waveform. Platform: |
Size: 16384 |
Author:Amr |
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Description: gps延迟锁定环中对热噪声的模拟，考虑了热噪声对跟踪精度的影响，很不错的-gps delay locked loop in the thermal noise of the simulation, taking into account thermal noise on the impact of tracking accuracy, very good Platform: |
Size: 1024 |
Author:ddgqg463haoiadu |
Hits:
Search - Delay locked loop