Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接,可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send. Platform: |
Size: 7168 |
Author:YongZhiLi |
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Description: UART16550兼容的串行通讯控制器,Verilog语言描述,采用Altera Cyclone系列芯片实现FPGA综合,因为FIFO部分利用到内部资源实现。已经在某项目中成功应用,特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced. Platform: |
Size: 10240 |
Author:David.Mr.Liu |
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Description: uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB Platform: |
Size: 205824 |
Author:libin |
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Description: Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings. Platform: |
Size: 6756352 |
Author:515666524 |
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Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s
(3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control
Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during
hardware and software flow control. With the FIFO Rdy register, the software gets the
status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide
the user with error indications, operational status, and modem interface control. System
interrupts may be tailored to meet user requirements. An internal loopback capability
allows on-board diagnostics. Platform: |
Size: 160768 |
Author:刘伟 |
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Description: 关于串口发送的verilog代码,实验中经常用到,已经用FIFO-it is about the uart transmit verilog code,very useful in experiment. Platform: |
Size: 3072 |
Author:李sir |
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Description: 自己编写的带有FIFO的UART串口发送模块,代码通过状态机实现,开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog Platform: |
Size: 2048 |
Author:wangzhongwei |
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Description: 串口接收模块,可以通过parameter,参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数,并根据缓冲的大小配置FIFO就可以使用。对帧错误(停止位不为高),检验错误和读FIFO超时(FIFO满的情况下,有新的数据到)等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data width and parity. Using Verilog. The user configured the parameters according to the serial port and configured FIFO according to the size of the buffer. The frame error (stop bit is not high), check errors, and read FIFO timeout (when FIFO is full,and new data come) and so on are examined.) Platform: |
Size: 4096 |
Author:老工程师
|
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Description: UART设计的VERILOG代码,具有FIFO功能,能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals) Platform: |
Size: 547840 |
Author:沐羽1996 |
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