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[Other resource] RS232uart(VHDL)

Description: 256字节深度的RS232串口程序,共分4个模块,顶层文件\\FIFO程序\\串口收和串口发.经过测试已用于产品.可靠!
Platform: | Size: 5377 | Author: 温海龙 | Hits:

[Other] S3C44B0X中文技术文档

Description:

 

介    绍
三星的S3C44B0X 16/32位RISC处理器被设计来为手持设备等提供一个低成本高性能的方案。
S3C44B0X提供以下配置：2.5V ARM7TDMI 内核带有8Kcache ;可选的internal SRAM;LCD Controller(最大支持256色STN，使用LCD专用DMA)；2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO； 2-ch general DMAs / 2-ch peripheral DMAs with external request pins； External memory controller (chip select logic, FP/ EDO/SDRAM controller)； 5-ch PWM timers & 1-ch internal timer；Watch Dog Timer；71 general purpose I/O ports / 8-ch external interrupt source； RTC with calendar function； 8-ch 10-bit ADC； 1-ch multi-master IIC-BUS controller； 1-ch IIS-BUS controller； Sync. SIO interface and On-chip clock generator with PLL.。
S3C44B0X采用一种新的三星ARM CPU嵌入总线结构-SAMBA2，最大达66MHZ。

Platform: | Size: 78690 | Author: ssunshine | Hits:

[OS Develop] C_code

Description: rtCell 实时微内核－具有下列功能： 1. 完全抢占的实时微内核结构，独立的内核栈，中断和系统调用均切换到内核栈执行； 2. 256(64、32)个优先级，0为最高优先级（系统保留），256(64、32)为空闲优先级； 3. 不同优先级任务完全抢占，同优先级之间可按先进先出或时间片轮转方式执行； -rtCell real-time micro-kernel- with the following features: 1. fully seize the real-time micro-kernel structure, independent kernel stack, interrupt and system calls are switched to the kernel stack implementation 2.256 (64,32) priority level , 0 as the highest priority (System reservation), 256 (64,32) for the idle priority 3. different priority tasks fully occupy the same priority can be FIFO or time between the film rotary manner
Platform: | Size: 108544 | Author: 阿斗 | Hits:

[VHDL-FPGA-Verilog] RS232uart(VHDL)

Description: 256字节深度的RS232串口程序,共分4个模块,顶层文件\FIFO程序\串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!
Platform: | Size: 5120 | Author: 温海龙 | Hits:

[SCM] Flash_ROM_lab

Description: 用SmartGen生成一个256*8的大小同步FIFO，并通过串口发送数据初始化FIFO。然后，再通过串口返回到上位机的串口调试程序显示，确认数据是否正确。-SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC serial port debugger display to confirm the data is correct.
Platform: | Size: 3072 | Author: 劳杰勇 | Hits:

[Other] ddr_usb

Description: 将256位数据宽度 通过两级FIFO 转成16位 使用XILINX的ISE10.1完成设计 此为工程文件 有仿真结果-The 256-bit data width conversion FIFO through the two 16-bit using the XILINX s ISE10.1 to complete the design documents for the works in this simulation results
Platform: | Size: 3467264 | Author: jiangyuhang | Hits:

[Software Engineering] fifo

Description: 用FPGA完成256*8的存储器的读写操作- complete reading and writing 256* 8 memory with FPGA
Platform: | Size: 1024 | Author: 刘珊 | Hits:

[VHDL-FPGA-Verilog] uart_EP3C16_FIFO

Description: Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
Platform: | Size: 6756352 | Author: 515666524 | Hits:

[VHDL-FPGA-Verilog] FIFO1

Description: 异步FIFO，实时给出读空和溢出指示，深度为256，宽度为8-Asynchronous FIFO, read real-time air and overflow indication is given
Platform: | Size: 1024 | Author: 丁剑 | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write an eight-bit data to RAM when the rising edge of read clock pulse, the judge read the signal is valid, from eight bits of data in RAM to a read out. When RAM is full of data to generate a full mark, can not go down RAM write data when the RAM data read empty an empty sign, can not read data from RAM.
Platform: | Size: 333824 | Author: 肖波 | Hits:

[Other] fifoVerilog

Description: 设计一个异步FIFO，完成数据平滑功能，FIFO的深度为256，宽度为8位，实时给出读空和溢出指示，写时钟为带间隔的100MHz，读时钟为5MHz，代码为了便于读阅，存放在word文档，可直接拷贝到quartus或者ise编译平台下使用-Design an asynchronous FIFO, complete data smoothing function, the depth of the FIFO 256, and the width is 8 bits, real read empty and overflow indication is given, the write clock for the 100MHz band interval, the read clock is 5MHz, the code in order to facilitate the read access, storage In the word document, can be directly copied to the quartus, or ise compile platform use
Platform: | Size: 11264 | Author: 钱雪荣 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 深度256的异步fifo 使用verilog语言编写的，能够实现简单的读写，存储功能！-256 the depth of asynchronous FIFO
Platform: | Size: 1024 | Author: 王先生 | Hits:

[VHDL-FPGA-Verilog] fifo_ip

Description: 定制fifo IP核，8位宽，256深度，实现数据的写入和读取-Custom fifo IP core, 8-bit wide, 256 deep, realize the writing and reading of data
Platform: | Size: 2048 | Author: | Hits:

[Other] page

Description: 模拟操作系统采用OPT、FIFO和LRU算法进行页面置换的过程。 设程序中地址范围为0到32767，采用随机数生成256个指令地址，满足50 的地址是顺序执行，25 向前跳，25 向后跳。为满足上述条件，可采取下列方法： 设d0 10000，第 n个指令地址为dn，第 n+1 个指令地址为dn+1 ，n的取值范围为0 到255。每次生成一个 1 到1024范围内的随机数a，如果a落在1 到512 范围内，则dn+1 dn+1。如果a落在513 到768范围内，则设置dn+1 为1 到dn范围内一个随机数。如果a落在769 到1024范围内，则设置dn+1 为dn到32767范围内一个随机数。 页面大小的取值范围为1K，2K，4K，8K，16K 。按照页面大小将指令地址转化为页号。对于相邻相同的页号，合并为一个。 分配给程序的内存块数取值范围为1 块，2 块，直到程序的页面数。 6、 分别采用OPT、FIFO 和LRU算法对页号序列进行调度，计算出对应的缺页中断率。 打印出页面大小、分配给程序的内存块数、算法名、对应的缺页中断率。 操作系统页面置换算法通过c++实现 -Simulation operating system uses OPT, FIFO and LRU page replacement algorithm process. Let the program addresses the range of 0 to 32767, using a random number generator 256 instruction address, the address is to meet 50 of the order, a 25 jump forward, jump back 25 . To meet the above conditions, you can take the following methods: Let d0 10000, n-th instruction address is dn, the first n+1 instruction address dn+1, n the range of 0-255. 1-1024 each generate a random number within a range, if a falls within the range of 1-512, the dn+1 dn+1. If a falls within the range of 513-768, set dn+1 within the range of 1 to dn a random number. If a falls within the range of 769-1024, is set to dn dn+1 to a random number within the range of 32767. Page size in the range of 1K, 2K, 4K, 8K, 16K. Follow the page size of the instruction address into the page number. For the same adjacent page numbers, into one. Memory blocks allocated to the program in the range of 1, 2, until the page number
Platform: | Size: 2643968 | Author: 黄keke | Hits:

[VHDL-FPGA-Verilog] [verilog]dcfifo_256x32

Description: Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.
Platform: | Size: 1024 | Author: ylwang | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)
Platform: | Size: 1024 | Author: chenxuan123456 | Hits:

[Other] SH6883

Description: The SH6883 is designed for high performance Low-speed USB devices. It contains an 8051 micro-controller, Low-Speed USB SIE, Transceiver and data FIFO, build-in 3.3V regulator, on-chip 8K bytes Mask ROM and internal 256 bytes data RAM, Time capture circuit, Base timer, programmable Watch-dog timer and Wake-up timer, 37 Selectable GPIO (on 48-pin LQFP package), support multiple type LED driving capability for different application, build-in internal 32KHz oscillator, POR and LVR circuit saving your external components cost
Platform: | Size: 2154879 | Author: simoon | Hits:

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